test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -mtriple=i386-linux-gnu -mattr=+bmi -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86

# test count trailing zeros for s16, s32, and s64

---
name:            test_cttz35
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
body:             |
  bb.1:
    ; X64-LABEL: name: test_cttz35
    ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
    ; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
    ; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
    ; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
    ; X64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738367
    ; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[CTTZ_ZERO_UNDEF]], [[C1]]
    ; X64-NEXT: RET 0, implicit [[AND]](s64)
    ;
    ; X86-LABEL: name: test_cttz35
    ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
    ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[C]]
    ; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[C1]]
    ; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
    ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
    ; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
    ; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
    ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
    ; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
    ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
    ; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
    ; X86-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; X86-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
    ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C4]]
    ; X86-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C5]]
    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[AND2]](s32)
    ; X86-NEXT: RET 0, implicit [[MV]](s64)
    %0(s64) = COPY $rdx
    %1:_(s35) = G_TRUNC %0(s64)
    %2:_(s35) = G_CTTZ %1
    %3:_(s64) = G_ZEXT %2
    RET 0, implicit %3
...
---
name:            test_cttz8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_cttz8
    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF]](s8)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 256
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[ANYEXT]], [[C]]
    ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[OR]](s16)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s16)
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](s8)
    %0:_(s8) = IMPLICIT_DEF
    %1:_(s8) = G_CTTZ %0
    %2:_(s8) = COPY %1(s8)
    RET 0, implicit %2
...
---
name:            test_cttz64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
body:             |
  bb.1:
    ; X64-LABEL: name: test_cttz64
    ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X64-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[DEF]](s64)
    ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTTZ]](s64)
    ; X64-NEXT: RET 0, implicit [[COPY]](s64)
    ;
    ; X86-LABEL: name: test_cttz64
    ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
    ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
    ; X86-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[UV1]](s32)
    ; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ]], [[C1]]
    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
    ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
    ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
    ; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
    ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF]]
    ; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
    ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
    ; X86-NEXT: RET 0, implicit [[COPY]](s64)
    %0:_(s64) = IMPLICIT_DEF
    %1:_(s64) = G_CTTZ %0
    %2:_(s64) = COPY %1(s64)
    RET 0, implicit %2
...
---
name:            test_cttz32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_cttz32
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
    ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[DEF]](s32)
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](s32)
    %0:_(s32) = IMPLICIT_DEF
    %1:_(s32) = G_CTTZ %0
    %2:_(s32) = COPY %1(s32)
    RET 0, implicit %2
...
---
name:            test_cttz16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_cttz16
    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
    ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s16) = G_CTTZ [[DEF]](s16)
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[CTTZ]](s16)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](s16)
    %0:_(s16) = IMPLICIT_DEF
    %1:_(s16) = G_CTTZ %0
    %2:_(s16) = COPY %1(s16)
    RET 0, implicit %2
...