test/CodeGen/RISCV/rvv/undef-subreg-range.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -O2 -mtriple riscv64 -riscv-enable-subreg-liveness \
# RUN:     -verify-machineinstrs -run-pass=riscv-expand-pseudo -o - 2>&1 \
# RUN:     | FileCheck %s
--- |
  define void @foo() #0 {
  entry:
    ret void
  }
...
---
name:            foo
alignment:       4
tracksRegLiveness: true
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 8,
      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true }
body:             |
  bb.0.entry:
    liveins: $v8m2, $x10, $x11
    ; CHECK-LABEL: name: foo
    ; CHECK: liveins: $v8m2, $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: VS2R_V $v8m2, $x10, implicit $v8m2_v10m2 :: (store unknown-size into %stack.0, align 8)
    ; CHECK-NEXT: $x10 = ADD $x10, $x11
    ; CHECK-NEXT: VS2R_V $v10m2, $x10, implicit $v8m2_v10m2 :: (store unknown-size into %stack.0, align 8)
    ; CHECK-NEXT: PseudoRET
    PseudoVSPILL2_M2 killed $v8m2_v10m2, killed $x10, killed $x11 :: (store unknown-size into %stack.0, align 8)
    PseudoRET

...