test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s

declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(iXLen);

declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
  <vscale x 1 x i8>,
  <vscale x 1 x i8>,
  <vscale x 1 x i8>,
  <vscale x 1 x i1>,
  iXLen, iXLen);

; Use unmasked instruction because the mask operand is allone mask
define <vscale x 1 x i8> @test0(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: test0:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT:    vadd.vv v8, v8, v9
; CHECK-NEXT:    ret
entry:
  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
    iXLen %2);
  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
    <vscale x 1 x i8> undef,
    <vscale x 1 x i8> %0,
    <vscale x 1 x i8> %1,
    <vscale x 1 x i1> %allone,
    iXLen %2, iXLen 1)

  ret <vscale x 1 x i8> %a
}

; Use an unmasked TAIL_AGNOSTIC instruction if the tie operand is IMPLICIT_DEF
define <vscale x 1 x i8> @test1(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: test1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT:    vadd.vv v8, v8, v9
; CHECK-NEXT:    ret
entry:
  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
    iXLen %2);
  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
    <vscale x 1 x i8> undef,
    <vscale x 1 x i8> %0,
    <vscale x 1 x i8> %1,
    <vscale x 1 x i1> %allone,
    iXLen %2, iXLen 0)

  ret <vscale x 1 x i8> %a
}

; Use an unmasked TU instruction because of the policy operand
define <vscale x 1 x i8> @test2(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: test2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT:    vadd.vv v8, v9, v10
; CHECK-NEXT:    ret
entry:
  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
    iXLen %3);
  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
    <vscale x 1 x i8> %0,
    <vscale x 1 x i8> %1,
    <vscale x 1 x i8> %2,
    <vscale x 1 x i1> %allone,
    iXLen %3, iXLen 0)

  ret <vscale x 1 x i8> %a
}

; Merge operand is dropped because of the policy operand
define <vscale x 1 x i8> @test3(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: test3:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT:    vadd.vv v8, v9, v10
; CHECK-NEXT:    ret
entry:
  %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
    iXLen %3);
  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
    <vscale x 1 x i8> %0,
    <vscale x 1 x i8> %1,
    <vscale x 1 x i8> %2,
    <vscale x 1 x i1> %allone,
    iXLen %3, iXLen 1)

  ret <vscale x 1 x i8> %a
}