test/CodeGen/RISCV/rvv/aliases.mir

# RUN: llc -mtriple riscv32 -mattr=+v -start-after riscv-expand-pseudo -o - %s | FileCheck %s
# RUN: llc -mtriple riscv64 -mattr=+v -start-after riscv-expand-pseudo -o - %s | FileCheck %s

--- |
  define void @vnot_mask_1() {
    ret void
  }
  define void @vnot_mask_2() {
    ret void
  }
  define void @vnot_no_mask_1() {
    ret void
  }
  define void @vnot_no_mask_2() {
    ret void
  }
...
---
name:            vnot_mask_1
body:             |
  bb.0:
    liveins: $v0, $v25

    ; CHECK-LABEL: vnot_mask_1:
    ; CHECK: vnot.v v25, v25, v0.t

    $v25 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl
...
---
name:            vnot_mask_2
body:             |
  bb.0:
    liveins: $v0, $v25

    ; CHECK-LABEL: vnot_mask_2:
    ; CHECK: vnot.v v1, v25, v0.t

    $v1 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl
...
---
name:            vnot_no_mask_1
body:             |
  bb.0:
    liveins: $v25

    ; CHECK-LABEL: vnot_no_mask_1:
    ; CHECK: vnot.v v25, v25

    $v25 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl
...
---
name:            vnot_no_mask_2
body:             |
  bb.0:
    liveins: $v25

    ; CHECK-LABEL: vnot_no_mask_2:
    ; CHECK: vnot.v v1, v25

    $v1 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl
...