test/CodeGen/X86/legalize-vec-assertzext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s

define i64 @split_assertzext(ptr %x) nounwind {
; CHECK-LABEL: split_assertzext:
; CHECK:       # %bb.0:
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    callq test@PLT
; CHECK-NEXT:    vextracti32x4 $3, %zmm1, %xmm0
; CHECK-NEXT:    vpextrq $1, %xmm0, %rax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %e = call <16 x i64> @test(), !range !0
  %d = extractelement <16 x i64> %e, i32 15
  ret i64 %d
}

define i64 @widen_assertzext(ptr %x) nounwind {
; CHECK-LABEL: widen_assertzext:
; CHECK:       # %bb.0:
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    callq test2@PLT
; CHECK-NEXT:    movb $127, %al
; CHECK-NEXT:    kmovw %eax, %k1
; CHECK-NEXT:    vpexpandq %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT:    vextracti32x4 $3, %zmm0, %xmm0
; CHECK-NEXT:    vmovq %xmm0, %rax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %e = call <7 x i64> @test2(), !range !0
  %d = extractelement <7 x i64> %e, i32 6
  ret i64 %d
}

declare  <16 x i64> @test()
declare  <7 x i64> @test2()
!0 = !{ i64 0, i64 2 }