| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+gfni | FileCheck %s --check-prefixes=GFNISSE |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+gfni | FileCheck %s --check-prefixes=GFNIAVX1OR2,GFNIAVX1 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+gfni | FileCheck %s --check-prefixes=GFNIAVX1OR2,GFNIAVX2 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+gfni | FileCheck %s --check-prefixes=GFNIAVX512 |
| |
| ; |
| ; 128 Bit Vector Funnel Shifts |
| ; |
| |
| define <16 x i8> @splatconstant_fshl_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind { |
| ; GFNISSE-LABEL: splatconstant_fshl_v16i8: |
| ; GFNISSE: # %bb.0: |
| ; GFNISSE-NEXT: psrlw $5, %xmm1 |
| ; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 |
| ; GFNISSE-NEXT: psllw $3, %xmm0 |
| ; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 |
| ; GFNISSE-NEXT: por %xmm1, %xmm0 |
| ; GFNISSE-NEXT: retq |
| ; |
| ; GFNIAVX1OR2-LABEL: splatconstant_fshl_v16i8: |
| ; GFNIAVX1OR2: # %bb.0: |
| ; GFNIAVX1OR2-NEXT: vpsrlw $5, %xmm1, %xmm1 |
| ; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 |
| ; GFNIAVX1OR2-NEXT: vpsllw $3, %xmm0, %xmm0 |
| ; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 |
| ; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 |
| ; GFNIAVX1OR2-NEXT: retq |
| ; |
| ; GFNIAVX512-LABEL: splatconstant_fshl_v16i8: |
| ; GFNIAVX512: # %bb.0: |
| ; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm2 |
| ; GFNIAVX512-NEXT: vpsrlw $5, %xmm1, %xmm0 |
| ; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0 |
| ; GFNIAVX512-NEXT: retq |
| %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) |
| ret <16 x i8> %res |
| } |
| declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) |
| |
| define <16 x i8> @splatconstant_fshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind { |
| ; GFNISSE-LABEL: splatconstant_fshr_v16i8: |
| ; GFNISSE: # %bb.0: |
| ; GFNISSE-NEXT: psrlw $7, %xmm1 |
| ; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 |
| ; GFNISSE-NEXT: paddb %xmm0, %xmm0 |
| ; GFNISSE-NEXT: por %xmm1, %xmm0 |
| ; GFNISSE-NEXT: retq |
| ; |
| ; GFNIAVX1OR2-LABEL: splatconstant_fshr_v16i8: |
| ; GFNIAVX1OR2: # %bb.0: |
| ; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm1, %xmm1 |
| ; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 |
| ; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 |
| ; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 |
| ; GFNIAVX1OR2-NEXT: retq |
| ; |
| ; GFNIAVX512-LABEL: splatconstant_fshr_v16i8: |
| ; GFNIAVX512: # %bb.0: |
| ; GFNIAVX512-NEXT: vpsrlw $7, %xmm1, %xmm1 |
| ; GFNIAVX512-NEXT: vpaddb %xmm0, %xmm0, %xmm0 |
| ; GFNIAVX512-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0 |
| ; GFNIAVX512-NEXT: retq |
| %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>) |
| ret <16 x i8> %res |
| } |
| declare <16 x i8> @llvm.fshr.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) |
| |
| ; |
| ; 256 Bit Vector Funnel Shifts |
| ; |
| |
| define <32 x i8> @splatconstant_fshl_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { |
| ; GFNISSE-LABEL: splatconstant_fshl_v32i8: |
| ; GFNISSE: # %bb.0: |
| ; GFNISSE-NEXT: psrlw $4, %xmm2 |
| ; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] |
| ; GFNISSE-NEXT: movdqa %xmm4, %xmm5 |
| ; GFNISSE-NEXT: pandn %xmm2, %xmm5 |
| ; GFNISSE-NEXT: psllw $4, %xmm0 |
| ; GFNISSE-NEXT: pand %xmm4, %xmm0 |
| ; GFNISSE-NEXT: por %xmm5, %xmm0 |
| ; GFNISSE-NEXT: psrlw $4, %xmm3 |
| ; GFNISSE-NEXT: psllw $4, %xmm1 |
| ; GFNISSE-NEXT: pand %xmm4, %xmm1 |
| ; GFNISSE-NEXT: pandn %xmm3, %xmm4 |
| ; GFNISSE-NEXT: por %xmm4, %xmm1 |
| ; GFNISSE-NEXT: retq |
| ; |
| ; GFNIAVX1-LABEL: splatconstant_fshl_v32i8: |
| ; GFNIAVX1: # %bb.0: |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 |
| ; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: retq |
| ; |
| ; GFNIAVX2-LABEL: splatconstant_fshl_v32i8: |
| ; GFNIAVX2: # %bb.0: |
| ; GFNIAVX2-NEXT: vpsrlw $4, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: retq |
| ; |
| ; GFNIAVX512-LABEL: splatconstant_fshl_v32i8: |
| ; GFNIAVX512: # %bb.0: |
| ; GFNIAVX512-NEXT: vpsllw $4, %ymm0, %ymm2 |
| ; GFNIAVX512-NEXT: vpsrlw $4, %ymm1, %ymm0 |
| ; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm2, %ymm0 |
| ; GFNIAVX512-NEXT: retq |
| %res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) |
| ret <32 x i8> %res |
| } |
| declare <32 x i8> @llvm.fshl.v32i8(<32 x i8>, <32 x i8>, <32 x i8>) |
| |
| define <32 x i8> @splatconstant_fshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind { |
| ; GFNISSE-LABEL: splatconstant_fshr_v32i8: |
| ; GFNISSE: # %bb.0: |
| ; GFNISSE-NEXT: psrlw $6, %xmm2 |
| ; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] |
| ; GFNISSE-NEXT: movdqa %xmm4, %xmm5 |
| ; GFNISSE-NEXT: pandn %xmm2, %xmm5 |
| ; GFNISSE-NEXT: psllw $2, %xmm0 |
| ; GFNISSE-NEXT: pand %xmm4, %xmm0 |
| ; GFNISSE-NEXT: por %xmm5, %xmm0 |
| ; GFNISSE-NEXT: psrlw $6, %xmm3 |
| ; GFNISSE-NEXT: psllw $2, %xmm1 |
| ; GFNISSE-NEXT: pand %xmm4, %xmm1 |
| ; GFNISSE-NEXT: pandn %xmm3, %xmm4 |
| ; GFNISSE-NEXT: por %xmm4, %xmm1 |
| ; GFNISSE-NEXT: retq |
| ; |
| ; GFNIAVX1-LABEL: splatconstant_fshr_v32i8: |
| ; GFNIAVX1: # %bb.0: |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $6, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $6, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 |
| ; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: retq |
| ; |
| ; GFNIAVX2-LABEL: splatconstant_fshr_v32i8: |
| ; GFNIAVX2: # %bb.0: |
| ; GFNIAVX2-NEXT: vpsrlw $6, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: retq |
| ; |
| ; GFNIAVX512-LABEL: splatconstant_fshr_v32i8: |
| ; GFNIAVX512: # %bb.0: |
| ; GFNIAVX512-NEXT: vpsllw $2, %ymm0, %ymm2 |
| ; GFNIAVX512-NEXT: vpsrlw $6, %ymm1, %ymm0 |
| ; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm2, %ymm0 |
| ; GFNIAVX512-NEXT: retq |
| %res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>) |
| ret <32 x i8> %res |
| } |
| declare <32 x i8> @llvm.fshr.v32i8(<32 x i8>, <32 x i8>, <32 x i8>) |
| |
| ; |
| ; 512 Bit Vector Funnel Shifts |
| ; |
| |
| define <64 x i8> @splatconstant_fshl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind { |
| ; GFNISSE-LABEL: splatconstant_fshl_v64i8: |
| ; GFNISSE: # %bb.0: |
| ; GFNISSE-NEXT: psrlw $7, %xmm4 |
| ; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] |
| ; GFNISSE-NEXT: pand %xmm8, %xmm4 |
| ; GFNISSE-NEXT: paddb %xmm0, %xmm0 |
| ; GFNISSE-NEXT: por %xmm4, %xmm0 |
| ; GFNISSE-NEXT: psrlw $7, %xmm5 |
| ; GFNISSE-NEXT: pand %xmm8, %xmm5 |
| ; GFNISSE-NEXT: paddb %xmm1, %xmm1 |
| ; GFNISSE-NEXT: por %xmm5, %xmm1 |
| ; GFNISSE-NEXT: psrlw $7, %xmm6 |
| ; GFNISSE-NEXT: pand %xmm8, %xmm6 |
| ; GFNISSE-NEXT: paddb %xmm2, %xmm2 |
| ; GFNISSE-NEXT: por %xmm6, %xmm2 |
| ; GFNISSE-NEXT: psrlw $7, %xmm7 |
| ; GFNISSE-NEXT: pand %xmm7, %xmm8 |
| ; GFNISSE-NEXT: paddb %xmm3, %xmm3 |
| ; GFNISSE-NEXT: por %xmm8, %xmm3 |
| ; GFNISSE-NEXT: retq |
| ; |
| ; GFNIAVX1-LABEL: splatconstant_fshl_v64i8: |
| ; GFNIAVX1: # %bb.0: |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 |
| ; GFNIAVX1-NEXT: vpsrlw $7, %xmm4, %xmm4 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4 |
| ; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2 |
| ; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 |
| ; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm4, %ymm0 |
| ; GFNIAVX1-NEXT: vorps %ymm2, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $7, %xmm3, %xmm3 |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 |
| ; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm3 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 |
| ; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 |
| ; GFNIAVX1-NEXT: vorps %ymm2, %ymm1, %ymm1 |
| ; GFNIAVX1-NEXT: retq |
| ; |
| ; GFNIAVX2-LABEL: splatconstant_fshl_v64i8: |
| ; GFNIAVX2: # %bb.0: |
| ; GFNIAVX2-NEXT: vpsrlw $7, %ymm2, %ymm2 |
| ; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm4 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] |
| ; GFNIAVX2-NEXT: vpand %ymm4, %ymm2, %ymm2 |
| ; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpsrlw $7, %ymm3, %ymm2 |
| ; GFNIAVX2-NEXT: vpand %ymm4, %ymm2, %ymm2 |
| ; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpor %ymm2, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: retq |
| ; |
| ; GFNIAVX512-LABEL: splatconstant_fshl_v64i8: |
| ; GFNIAVX512: # %bb.0: |
| ; GFNIAVX512-NEXT: vpsrlw $7, %zmm1, %zmm1 |
| ; GFNIAVX512-NEXT: vpaddb %zmm0, %zmm0, %zmm0 |
| ; GFNIAVX512-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0 |
| ; GFNIAVX512-NEXT: retq |
| %res = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) |
| ret <64 x i8> %res |
| } |
| declare <64 x i8> @llvm.fshl.v64i8(<64 x i8>, <64 x i8>, <64 x i8>) |
| |
| define <64 x i8> @splatconstant_fshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind { |
| ; GFNISSE-LABEL: splatconstant_fshr_v64i8: |
| ; GFNISSE: # %bb.0: |
| ; GFNISSE-NEXT: psrlw $2, %xmm4 |
| ; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192] |
| ; GFNISSE-NEXT: movdqa %xmm8, %xmm9 |
| ; GFNISSE-NEXT: pandn %xmm4, %xmm9 |
| ; GFNISSE-NEXT: psllw $6, %xmm0 |
| ; GFNISSE-NEXT: pand %xmm8, %xmm0 |
| ; GFNISSE-NEXT: por %xmm9, %xmm0 |
| ; GFNISSE-NEXT: psrlw $2, %xmm5 |
| ; GFNISSE-NEXT: movdqa %xmm8, %xmm4 |
| ; GFNISSE-NEXT: pandn %xmm5, %xmm4 |
| ; GFNISSE-NEXT: psllw $6, %xmm1 |
| ; GFNISSE-NEXT: pand %xmm8, %xmm1 |
| ; GFNISSE-NEXT: por %xmm4, %xmm1 |
| ; GFNISSE-NEXT: psrlw $2, %xmm6 |
| ; GFNISSE-NEXT: movdqa %xmm8, %xmm4 |
| ; GFNISSE-NEXT: pandn %xmm6, %xmm4 |
| ; GFNISSE-NEXT: psllw $6, %xmm2 |
| ; GFNISSE-NEXT: pand %xmm8, %xmm2 |
| ; GFNISSE-NEXT: por %xmm4, %xmm2 |
| ; GFNISSE-NEXT: psrlw $2, %xmm7 |
| ; GFNISSE-NEXT: psllw $6, %xmm3 |
| ; GFNISSE-NEXT: pand %xmm8, %xmm3 |
| ; GFNISSE-NEXT: pandn %xmm7, %xmm8 |
| ; GFNISSE-NEXT: por %xmm8, %xmm3 |
| ; GFNISSE-NEXT: retq |
| ; |
| ; GFNIAVX1-LABEL: splatconstant_fshr_v64i8: |
| ; GFNIAVX1: # %bb.0: |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 |
| ; GFNIAVX1-NEXT: vpsrlw $2, %xmm4, %xmm4 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63] |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4 |
| ; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 |
| ; GFNIAVX1-NEXT: vpsllw $6, %xmm4, %xmm4 |
| ; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192] |
| ; GFNIAVX1-NEXT: vpand %xmm6, %xmm4, %xmm4 |
| ; GFNIAVX1-NEXT: vpsllw $6, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vpand %xmm6, %xmm0, %xmm0 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: vorps %ymm2, %ymm0, %ymm0 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 |
| ; GFNIAVX1-NEXT: vpsrlw $2, %xmm3, %xmm3 |
| ; GFNIAVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 |
| ; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 |
| ; GFNIAVX1-NEXT: vpsllw $6, %xmm3, %xmm3 |
| ; GFNIAVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 |
| ; GFNIAVX1-NEXT: vpsllw $6, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vpand %xmm6, %xmm1, %xmm1 |
| ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 |
| ; GFNIAVX1-NEXT: vorps %ymm2, %ymm1, %ymm1 |
| ; GFNIAVX1-NEXT: retq |
| ; |
| ; GFNIAVX2-LABEL: splatconstant_fshr_v64i8: |
| ; GFNIAVX2: # %bb.0: |
| ; GFNIAVX2-NEXT: vpsrlw $2, %ymm2, %ymm2 |
| ; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm4 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192] |
| ; GFNIAVX2-NEXT: vpandn %ymm2, %ymm4, %ymm2 |
| ; GFNIAVX2-NEXT: vpsllw $6, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpand %ymm4, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0 |
| ; GFNIAVX2-NEXT: vpsrlw $2, %ymm3, %ymm2 |
| ; GFNIAVX2-NEXT: vpandn %ymm2, %ymm4, %ymm2 |
| ; GFNIAVX2-NEXT: vpsllw $6, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpand %ymm4, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: vpor %ymm2, %ymm1, %ymm1 |
| ; GFNIAVX2-NEXT: retq |
| ; |
| ; GFNIAVX512-LABEL: splatconstant_fshr_v64i8: |
| ; GFNIAVX512: # %bb.0: |
| ; GFNIAVX512-NEXT: vpsllw $6, %zmm0, %zmm2 |
| ; GFNIAVX512-NEXT: vpsrlw $2, %zmm1, %zmm0 |
| ; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm2, %zmm0 |
| ; GFNIAVX512-NEXT: retq |
| %res = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>) |
| ret <64 x i8> %res |
| } |
| declare <64 x i8> @llvm.fshr.v64i8(<64 x i8>, <64 x i8>, <64 x i8>) |