test/CodeGen/X86/fsetcc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

define i8 @PR43088(double, double) nounwind {
; CHECK-LABEL: PR43088:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    ucomisd %xmm1, %xmm0
; CHECK-NEXT:    movl $0, %eax
; CHECK-NEXT:    adcb $1, %al
; CHECK-NEXT:    ucomisd %xmm1, %xmm0
; CHECK-NEXT:    sbbl %ecx, %ecx
; CHECK-NEXT:    ucomisd %xmm0, %xmm1
; CHECK-NEXT:    movzbl %al, %eax
; CHECK-NEXT:    cmovael %ecx, %eax
; CHECK-NEXT:    # kill: def $al killed $al killed $eax
; CHECK-NEXT:    retq
start:
    %2 = fcmp ole double %0, %1
    %3 = fcmp oge double %0, %1
    %spec.select1.i = select i1 %3, i8 1, i8 2
    %not..i = xor i1 %3, true
    %spec.select.i = sext i1 %not..i to i8
    %_0.0.i = select i1 %2, i8 %spec.select.i, i8 %spec.select1.i
    ret i8 %_0.0.i
}