test/CodeGen/X86/fold-load-vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s

; rdar://12721174
; We should not fold movss into pshufd since pshufd expects m128 while movss
; loads from m32.
define void @sample_test(ptr %source, ptr %dest) nounwind {
; CHECK-LABEL: sample_test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    subq $24, %rsp
; CHECK-NEXT:    movq %rdi, {{[0-9]+}}(%rsp)
; CHECK-NEXT:    movq %rsi, {{[0-9]+}}(%rsp)
; CHECK-NEXT:    xorps %xmm0, %xmm0
; CHECK-NEXT:    movlps %xmm0, (%rsp)
; CHECK-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT:    movlps %xmm0, (%rsp)
; CHECK-NEXT:    movlps %xmm0, (%rsi)
; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT:    movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-NEXT:    callq ext@PLT
; CHECK-NEXT:    addq $24, %rsp
; CHECK-NEXT:    retq
entry:
  %source.addr = alloca ptr, align 8
  %dest.addr = alloca ptr, align 8
  %tmp = alloca <2 x float>, align 8
  store ptr %source, ptr %source.addr, align 8
  store ptr %dest, ptr %dest.addr, align 8
  store <2 x float> zeroinitializer, ptr %tmp, align 8
  %0 = load ptr, ptr %source.addr, align 8
  %1 = load <4 x float>, ptr %0, align 16
  %2 = extractelement <4 x float> %1, i32 0
  %3 = load <2 x float>, ptr %tmp, align 8
  %4 = insertelement <2 x float> %3, float %2, i32 1
  store <2 x float> %4, ptr %tmp, align 8
  %5 = load <2 x float>, ptr %tmp, align 8
  %6 = load ptr, ptr %dest.addr, align 8
  store <2 x float> %5, ptr %6, align 8
  %7 = load ptr, ptr %dest.addr, align 8
  %8 = load <2 x float>, ptr %7, align 8
  %vecext = extractelement <2 x float> %8, i32 0
  %9 = load ptr, ptr %dest.addr, align 8
  %10 = load <2 x float>, ptr %9, align 8
  %vecext4 = extractelement <2 x float> %10, i32 1
  call void @ext(float %vecext, float %vecext4)
  ret void
}
declare void @ext(float, float)