test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s

# test vpand

---
name:            test_and_v8s32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
  - { id: 2, class: _, preferred-register: '' }
body:             |
  bb.1:

    ; CHECK-LABEL: name: test_and_v8s32
    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[AND]](<8 x s32>)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
    %0:_(<8 x s32>) = IMPLICIT_DEF
    %1:_(<8 x s32>) = G_AND %0, %0
    %2:_(<8 x s32>) = COPY %1(<8 x s32>)
    RET 0, implicit %2
...
---
name:            test_and_v4s64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
  - { id: 2, class: _, preferred-register: '' }
body:             |
  bb.1:

    ; CHECK-LABEL: name: test_and_v4s64
    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[AND]](<4 x s64>)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
    %0:_(<4 x s64>) = IMPLICIT_DEF
    %1:_(<4 x s64>) = G_AND %0, %0
    %2:_(<4 x s64>) = COPY %1(<4 x s64>)
    RET 0, implicit %2
...
---
name:            test_xor_v4s64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_xor_v4s64
    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[XOR]](<4 x s64>)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
    %0:_(<4 x s64>) = IMPLICIT_DEF
    %1:_(<4 x s64>) = G_XOR %0, %0
    %2:_(<4 x s64>) = COPY %1(<4 x s64>)
    RET 0, implicit %2

...
---
name:            test_xor_v8s32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_xor_v8s32
    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[XOR]](<8 x s32>)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
    %0:_(<8 x s32>) = IMPLICIT_DEF
    %1:_(<8 x s32>) = G_XOR %0, %0
    %2:_(<8 x s32>) = COPY %1(<8 x s32>)
    RET 0, implicit %2

...
---
name:            test_or_v4s64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_or_v4s64
    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[OR]](<4 x s64>)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
    %0:_(<4x s64>) = IMPLICIT_DEF
    %1:_(<4x s64>) = G_OR %0, %0
    %2:_(<4x s64>) = COPY %1(<4x s64>)
    RET 0, implicit %2

...
---
name:            test_or_v8s32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_or_v8s32
    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF]]
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[OR]](<8 x s32>)
    ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
    %0:_(<8x s32>) = IMPLICIT_DEF
    %1:_(<8x s32>) = G_OR %0, %0
    %2:_(<8x s32>) = COPY %1(<8x s32>)
    RET 0, implicit %2

...