Sign in
llvm
/
llvm-project
/
llvm
/
dd429fa8c88bd8a1f416ab7a456b0ac984f99473
/
.
/
test
/
CodeGen
/
Hexagon
/
vect
/
vect-vsubh-1.ll
blob: c1f87bf090d6762668d434c2b382c52fbec75fea [
file
] [
log
] [
blame
]
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vsubh
define
<
4
x
i16
>
@t_i4x16
(<
4
x
i16
>
%a
,
<
4
x
i16
>
%b
)
nounwind
{
entry
:
%0
=
sub
<
4
x
i16
>
%a
,
%b
ret
<
4
x
i16
>
%0
}