[RISCV] Don't use li+sh3add for constants that can use lui+add.
If we're adding a constant that can't use addi we try a few tricks,
one of which is using li+sh3add. We should not do this if lui+add
would work. For example adding 8192. Using sh3add prevents folding
a sext.w to form addw, thus increasing instruction count.
GitOrigin-RevId: 75c64c7c4e40ec9bc16d90fee46353628d08d62d
diff --git a/lib/Target/RISCV/RISCVInstrInfoZb.td b/lib/Target/RISCV/RISCVInstrInfoZb.td
index 72122d6..1a7539f 100644
--- a/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -237,17 +237,17 @@
if (!N->hasOneUse())
return false;
int64_t C = N->getSExtValue();
- // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
- return !isInt<13>(C) && isShiftedInt<12, 2>(C);
+ // Skip if C is simm12, an lui, or can be optimized by the PatLeaf AddiPair.
+ return !isInt<13>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 2>(C);
}]>;
def CSImm12MulBy8 : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
int64_t C = N->getSExtValue();
- // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair or
+ // Skip if C is simm12, an lui or can be optimized by the PatLeaf AddiPair or
// CSImm12MulBy4.
- return !isInt<14>(C) && isShiftedInt<12, 3>(C);
+ return !isInt<14>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 3>(C);
}]>;
def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
diff --git a/test/CodeGen/RISCV/rv32zba.ll b/test/CodeGen/RISCV/rv32zba.ll
index 35b0920..f39fa6a6 100644
--- a/test/CodeGen/RISCV/rv32zba.ll
+++ b/test/CodeGen/RISCV/rv32zba.ll
@@ -561,6 +561,16 @@
ret i32 %c
}
+define i32 @add8192(i32 %a) {
+; CHECK-LABEL: add8192:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: ret
+ %c = add i32 %a, 8192
+ ret i32 %c
+}
+
define i32 @addshl_5_6(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_6:
; RV32I: # %bb.0:
diff --git a/test/CodeGen/RISCV/rv64zba.ll b/test/CodeGen/RISCV/rv64zba.ll
index 0ba1741..cd03b23 100644
--- a/test/CodeGen/RISCV/rv64zba.ll
+++ b/test/CodeGen/RISCV/rv64zba.ll
@@ -1116,6 +1116,28 @@
ret i64 %c
}
+; Make sure we prefer LUI for the 8192 instead of using sh3add.
+define signext i32 @add8192_i32(i32 signext %a) {
+; CHECK-LABEL: add8192_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 2
+; CHECK-NEXT: addw a0, a0, a1
+; CHECK-NEXT: ret
+ %c = add i32 %a, 8192
+ ret i32 %c
+}
+
+; Make sure we prefer LUI for the 8192 instead of using sh3add.
+define i64 @add8192(i64 %a) {
+; CHECK-LABEL: add8192:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: ret
+ %c = add i64 %a, 8192
+ ret i64 %c
+}
+
define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_6:
; RV64I: # %bb.0:
