test/CodeGen/RISCV/get-register-noreserve.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s

define i32 @get_stack() nounwind {
; CHECK-LABEL: get_stack:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    mv a0, sp
; CHECK-NEXT:    ret
entry:
  %sp = call i32 @llvm.read_register.i32(metadata !0)
  ret i32 %sp
}

define void @set_stack(i32 %val) nounwind {
; CHECK-LABEL: set_stack:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    mv sp, a0
; CHECK-NEXT:    ret
entry:
  call void @llvm.write_register.i32(metadata !0, i32 %val)
  ret void
}

define i32 @get_tp_arch_name() nounwind {
; CHECK-LABEL: get_tp_arch_name:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    mv a0, tp
; CHECK-NEXT:    ret
entry:
  %sp = call i32 @llvm.read_register.i32(metadata !1)
  ret i32 %sp
}

define i32 @get_csr_vlenb() nounwind {
; CHECK-LABEL: get_csr_vlenb:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    csrr a0, vlenb
; CHECK-NEXT:    ret
entry:
  %sp = call i32 @llvm.read_register.i32(metadata !2)
  ret i32 %sp
}


declare i32 @llvm.read_register.i32(metadata) nounwind
declare void @llvm.write_register.i32(metadata, i32) nounwind

!0 = !{!"sp\00"}
!1 = !{!"x4\00"}
!2 = !{!"vlenb"}