test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# REQUIRES: asserts
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-regalloc -misched-only-block=999 -start-before=machine-scheduler -stop-after=greedy,0 -o - %s | FileCheck %s

# This run line is a total hack to get the live intervals to make it
# to the verifier. This requires asserts to use
# -misched-only-block. We use the scheduler only because -start-before
# doesn't see si-optimize-exec-masking-pre-ra unless the scheduler is
# part of the pass pipeline.

---
name: subreg_value_undef
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: subreg_value_undef
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
  ; CHECK-NEXT:   [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
  ; CHECK-NEXT:   undef %2.sub1:sgpr_128 = S_MOV_B32 -1
  ; CHECK-NEXT:   $vcc_lo = S_ANDN2_B32 $exec_lo, undef %2.sub0, implicit-def dead $scc
  ; CHECK-NEXT:   %2.sub1:sgpr_128 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_NOP 0, implicit %2.sub1
  bb.0:
    liveins: $sgpr0_sgpr1
    %0:sgpr_64 = COPY $sgpr0_sgpr1
    %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
    undef %2.sub1:sgpr_128 = S_MOV_B32 -1
    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %2.sub0, implicit $exec
    %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
    $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
    %2.sub1:sgpr_128 = COPY %1.sub0
    S_CBRANCH_VCCNZ %bb.1, implicit $vcc

  bb.1:
    S_NOP 0, implicit %2.sub1
...

---
name: needs_distribute_0
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: needs_distribute_0
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
  ; CHECK-NEXT:   [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
  ; CHECK-NEXT:   undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
  ; CHECK-NEXT:   $vcc_lo = S_ANDN2_B32 $exec_lo, %2.sub0, implicit-def dead $scc
  ; CHECK-NEXT:   dead %2.sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  bb.0:
    liveins: $sgpr0_sgpr1
    %0:sgpr_64 = COPY $sgpr0_sgpr1
    %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
    undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
    %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
    $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
    %2.sub1:sreg_64_xexec = COPY %1.sub0
    S_CBRANCH_VCCNZ %bb.1, implicit $vcc

  bb.1:
...

---
name: needs_distribute_1
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: needs_distribute_1
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
  ; CHECK-NEXT:   [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
  ; CHECK-NEXT:   undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
  ; CHECK-NEXT:   $vcc_lo = S_ANDN2_B32 $exec_lo, %2.sub0, implicit-def dead $scc
  ; CHECK-NEXT:   %2.sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_NOP 0, implicit %2.sub1
  bb.0:
    liveins: $sgpr0_sgpr1
    %0:sgpr_64 = COPY $sgpr0_sgpr1
    %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
    undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
    %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
    $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
    %2.sub1:sreg_64_xexec = COPY %1.sub0
    S_CBRANCH_VCCNZ %bb.1, implicit $vcc

  bb.1:
    S_NOP 0, implicit %2.sub1
...

---
name: needs_distribute_2
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: needs_distribute_2
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
  ; CHECK-NEXT:   [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
  ; CHECK-NEXT:   undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
  ; CHECK-NEXT:   $vcc_lo = S_ANDN2_B32 $exec_lo, %2.sub0, implicit-def dead $scc
  ; CHECK-NEXT:   %2.sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_NOP 0, implicit %2
  bb.0:
    liveins: $sgpr0_sgpr1
    %0:sgpr_64 = COPY $sgpr0_sgpr1
    %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
    undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
    %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
    $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
    %2.sub1:sreg_64_xexec = COPY %1.sub0
    S_CBRANCH_VCCNZ %bb.1, implicit $vcc

  bb.1:
    S_NOP 0, implicit %2
...

---
name: needs_distribute_3
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: needs_distribute_3
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr0_sgpr1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
  ; CHECK-NEXT:   [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)
  ; CHECK-NEXT:   undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
  ; CHECK-NEXT:   $vcc_lo = S_ANDN2_B32 $exec_lo, %2.sub0, implicit-def dead $scc
  ; CHECK-NEXT:   %2.sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   S_NOP 0, implicit %2.sub0
  bb.0:
    liveins: $sgpr0_sgpr1
    %0:sgpr_64 = COPY $sgpr0_sgpr1
    %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)
    undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1
    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec
    %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec
    $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc
    %2.sub1:sreg_64_xexec = COPY %1.sub0
    S_CBRANCH_VCCNZ %bb.1, implicit $vcc

  bb.1:
    S_NOP 0, implicit %2.sub0
...