test/CodeGen/AMDGPU/fold-cndmask-wave32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s

---
name:            fold_cndmask
tracksRegLiveness: true
registers:
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: fold_cndmask
    ; CHECK: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
    %0:sreg_32_xm0_xexec = IMPLICIT_DEF
    %1:sreg_32 = S_MOV_B32 0
    %2:vgpr_32 = COPY %1:sreg_32
    %3:vgpr_32 = V_CNDMASK_B32_e64 0, %1:sreg_32, 0, %2:vgpr_32, %0:sreg_32_xm0_xexec, implicit $exec
    S_ENDPGM 0, implicit %3
...