test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=regbankselect %s -o - | FileCheck -check-prefix=SI %s

--- |

  define amdgpu_ps i96 @split_smrd_load_range(i96 addrspace(4)* %ptr) {
    %load = load i96, i96 addrspace(4)* %ptr, !range !0
    ret i96 %load
  }

  define amdgpu_ps <3 x i32> @split_smrd_load_tbaa(<3 x i32> addrspace(4)* %ptr) {
    %load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, !tbaa !1
    ret <3 x i32> %load
  }

  !0 = !{i96 0, i96 9223372036854775808}
  !1 = !{!"omnipotent char", !2}
  !2 = !{!"Simple C/C++ TBAA"}
...

# Make sure range metadata is not preserved when widening loads, but
# tbaa is.

---
name: split_smrd_load_range
legalized: true
body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; SI-LABEL: name: split_smrd_load_range
    ; SI: liveins: $sgpr0_sgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; SI-NEXT: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), addrspace 4)
    ; SI-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; SI-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; SI-NEXT: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s32) from unknown-address + 8, align 8, addrspace 4)
    ; SI-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
    ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
    ; SI-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<3 x s32>) = G_LOAD %0 :: (load (<3 x s32>), align 8, addrspace 4, !range !0)
    $sgpr0_sgpr1_sgpr2 = COPY %1

...

---
name: split_smrd_load_tbaa
legalized: true
body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; SI-LABEL: name: split_smrd_load_tbaa
    ; SI: liveins: $sgpr0_sgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; SI-NEXT: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), !tbaa !2, addrspace 4)
    ; SI-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; SI-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; SI-NEXT: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s32) from unknown-address + 8, align 8, !tbaa !2, addrspace 4)
    ; SI-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
    ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
    ; SI-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<3 x s32>) = G_LOAD %0 :: (load (<3 x s32>), align 8, addrspace 4, !tbaa !1)
    $sgpr0_sgpr1_sgpr2 = COPY %1

...