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| * Automatically generated file, do not edit! * |
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| .. _amdgpu_synid_gfx1030_soffset_d01a5c: |
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| soffset |
| ======= |
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| An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate. |
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| Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both. |
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| *Size:* 1 dword. |
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| *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>` |
