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llvm
/
llvm-project
/
llvm
/
cb91488c56bfda4b5d40c891c0ba09dfe9c34542
/
.
/
test
/
CodeGen
/
Hexagon
/
vect
/
vect-vaddh-1.ll
blob: 1b43d4fb6cc8615f6940a633b2641b91135c6982 [
file
]
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vaddh
define
<
4
x
i16
>
@t_i4x16
(<
4
x
i16
>
%a
,
<
4
x
i16
>
%b
)
nounwind
{
entry
:
%0
=
add
<
4
x
i16
>
%a
,
%b
ret
<
4
x
i16
>
%0
}