test/CodeGen/AArch64/fp8-sve-cvt-cvtlt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s
; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s

target triple = "aarch64-linux"

define <vscale x 8 x bfloat> @cvt1_bf16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvt1_bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bf1cvt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x bfloat> %r
}

define <vscale x 8 x bfloat> @cvt2_bf16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvt2_bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bf2cvt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x bfloat> %r
}

define <vscale x 8 x bfloat> @cvtlt1_bf16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvtlt1_bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bf1cvtlt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x bfloat> %r
}

define <vscale x 8 x bfloat> @cvtlt2_bf16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvtlt2_bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bf2cvtlt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x bfloat> %r
}

define <vscale x 8 x half> @cvt1_f16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvt1_f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    f1cvt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x half> %r
}

define <vscale x 8 x half> @cvt2_f16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvt2_f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    f2cvt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x half> %r
}


define <vscale x 8 x half> @cvtlt1_f16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvtlt1_f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    f1cvtlt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x half> %r
}

define <vscale x 8 x half> @cvtlt2_f16(<vscale x 16 x i8> %s) {
; CHECK-LABEL: cvtlt2_f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    f2cvtlt z0.h, z0.b
; CHECK-NEXT:    ret
    %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %s)
    ret <vscale x 8 x half> %r
}