test/CodeGen/AMDGPU/early-term.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-insert-skips -verify-machineinstrs  %s -o - | FileCheck %s

--- |
  define amdgpu_ps void @early_term_scc0_end_block() {
    ret void
  }

  define amdgpu_ps void @early_term_scc0_next_terminator() {
    ret void
  }

  define amdgpu_ps void @early_term_scc0_in_block() {
    ret void
  }

  define amdgpu_gs void @early_term_scc0_gs() {
    ret void
  }

  define amdgpu_cs void @early_term_scc0_cs() {
    ret void
  }
...

---
name: early_term_scc0_end_block
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr0' }
  - { reg: '$sgpr1' }
body: |
  ; CHECK-LABEL: name: early_term_scc0_end_block
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
  ; CHECK:   liveins: $sgpr0, $sgpr1
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
  ; CHECK:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK: bb.1:
  ; CHECK:   liveins: $vgpr0
  ; CHECK:   EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
  ; CHECK:   S_ENDPGM 0
  ; CHECK: bb.2:
  ; CHECK:   $exec_lo = S_MOV_B32 0
  ; CHECK:   EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec
  ; CHECK:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $sgpr1
    successors: %bb.1

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
    SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec

  bb.1:
    liveins: $vgpr0
    EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
    S_ENDPGM 0
...

---
name: early_term_scc0_next_terminator
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr0' }
  - { reg: '$sgpr1' }
body: |
  ; CHECK-LABEL: name: early_term_scc0_next_terminator
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.2(0x80000000), %bb.3(0x00000000)
  ; CHECK:   liveins: $sgpr0, $sgpr1
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
  ; CHECK:   S_CBRANCH_SCC0 %bb.3, implicit $scc
  ; CHECK:   S_BRANCH %bb.2
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 1, implicit $exec
  ; CHECK: bb.2:
  ; CHECK:   liveins: $vgpr0
  ; CHECK:   EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
  ; CHECK:   S_ENDPGM 0
  ; CHECK: bb.3:
  ; CHECK:   $exec_lo = S_MOV_B32 0
  ; CHECK:   EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec
  ; CHECK:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $sgpr1
    successors: %bb.2

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
    SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
    S_BRANCH %bb.2

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 1, implicit $exec
    S_BRANCH %bb.2

  bb.2:
    liveins: $vgpr0
    EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
    S_ENDPGM 0
...

---
name: early_term_scc0_in_block
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr0' }
  - { reg: '$sgpr1' }
body: |
  ; CHECK-LABEL: name: early_term_scc0_in_block
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   liveins: $sgpr0, $sgpr1
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
  ; CHECK:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK: bb.3:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $vgpr0, $scc
  ; CHECK:   $vgpr1 = V_MOV_B32_e32 1, implicit $exec
  ; CHECK: bb.1:
  ; CHECK:   liveins: $vgpr0, $vgpr1
  ; CHECK:   EXP 1, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
  ; CHECK:   EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
  ; CHECK:   S_ENDPGM 0
  ; CHECK: bb.2:
  ; CHECK:   $exec_lo = S_MOV_B32 0
  ; CHECK:   EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec
  ; CHECK:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $sgpr1
    successors: %bb.1

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
    SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
    $vgpr1 = V_MOV_B32_e32 1, implicit $exec

  bb.1:
    liveins: $vgpr0, $vgpr1
    EXP 1, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
    S_ENDPGM 0
...

---
name: early_term_scc0_gs
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr0' }
  - { reg: '$sgpr1' }
body: |
  ; CHECK-LABEL: name: early_term_scc0_gs
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $sgpr0, $sgpr1
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
  ; CHECK: bb.1:
  ; CHECK:   liveins: $vgpr0
  ; CHECK:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $sgpr1
    successors: %bb.1

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
    SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec

  bb.1:
    liveins: $vgpr0
    S_ENDPGM 0
...

---
name: early_term_scc0_cs
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr0' }
  - { reg: '$sgpr1' }
body: |
  ; CHECK-LABEL: name: early_term_scc0_cs
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
  ; CHECK:   liveins: $sgpr0, $sgpr1
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
  ; CHECK:   S_CBRANCH_SCC0 %bb.2, implicit $scc
  ; CHECK: bb.1:
  ; CHECK:   liveins: $vgpr0
  ; CHECK:   S_ENDPGM 0
  ; CHECK: bb.2:
  ; CHECK:   $exec_lo = S_MOV_B32 0
  ; CHECK:   S_ENDPGM 0
  bb.0:
    liveins: $sgpr0, $sgpr1
    successors: %bb.1

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
    SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec

  bb.1:
    liveins: $vgpr0
    S_ENDPGM 0
...