| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s |
| |
| --- |
| name: test_rsq_clamp_flags_ieee_on_f32 |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| mode: |
| ieee: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; SI-LABEL: name: test_rsq_clamp_flags_ieee_on_f32 |
| ; SI: liveins: $vgpr0 |
| ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; SI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32) |
| ; SI: $vgpr0 = COPY [[INT]](s32) |
| ; VI-LABEL: name: test_rsq_clamp_flags_ieee_on_f32 |
| ; VI: liveins: $vgpr0 |
| ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; VI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32) |
| ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000 |
| ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]] |
| ; VI: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000 |
| ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]] |
| ; VI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0 |
| $vgpr0 = COPY %1 |
| ... |
| |
| --- |
| name: test_rsq_clamp_flags_ieee_off_f32 |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| mode: |
| ieee: false |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; SI-LABEL: name: test_rsq_clamp_flags_ieee_off_f32 |
| ; SI: liveins: $vgpr0 |
| ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; SI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32) |
| ; SI: $vgpr0 = COPY [[INT]](s32) |
| ; VI-LABEL: name: test_rsq_clamp_flags_ieee_off_f32 |
| ; VI: liveins: $vgpr0 |
| ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; VI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32) |
| ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000 |
| ; VI: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]] |
| ; VI: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000 |
| ; VI: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]] |
| ; VI: $vgpr0 = COPY [[FMAXNUM]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0 |
| $vgpr0 = COPY %1 |
| ... |