| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 |
| ; RUN: opt -S -loop-reduce < %s | FileCheck %s |
| |
| target triple = "x86_64-unknown-unknown" |
| target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" |
| |
| define void @incorrect_offset_scaling(i1 %c, i1 %c2, i1 %c3, ptr %p, i64, ptr) { |
| ; CHECK-LABEL: define void @incorrect_offset_scaling( |
| ; CHECK-SAME: i1 [[C:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]], ptr [[P:%.*]], i64 [[TMP0:%.*]], ptr [[TMP1:%.*]]) { |
| ; CHECK-NEXT: top: |
| ; CHECK-NEXT: br label [[L:%.*]] |
| ; CHECK: L.loopexit: |
| ; CHECK-NEXT: br label [[L_BACKEDGE:%.*]] |
| ; CHECK: L: |
| ; CHECK-NEXT: br i1 [[C]], label [[L_BACKEDGE]], label [[L1_PREHEADER:%.*]] |
| ; CHECK: L.backedge: |
| ; CHECK-NEXT: br label [[L]] |
| ; CHECK: L1.preheader: |
| ; CHECK-NEXT: br label [[L1:%.*]] |
| ; CHECK: L1: |
| ; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ 0, [[L1_PREHEADER]] ], [ [[LSR_IV_NEXT:%.*]], [[L2:%.*]] ] |
| ; CHECK-NEXT: br label [[IDXEND_8:%.*]] |
| ; CHECK: L2: |
| ; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], 1 |
| ; CHECK-NEXT: br i1 [[C2]], label [[L_LOOPEXIT:%.*]], label [[L1]] |
| ; CHECK: if6: |
| ; CHECK-NEXT: [[R2:%.*]] = add i64 [[TMP0]], -1 |
| ; CHECK-NEXT: [[R3:%.*]] = load i64, ptr [[TMP1]], align 8 |
| ; CHECK-NEXT: br label [[IB:%.*]] |
| ; CHECK: idxend.8: |
| ; CHECK-NEXT: br i1 [[C3]], label [[IF6:%.*]], label [[L2]] |
| ; CHECK: ib: |
| ; CHECK-NEXT: [[R4:%.*]] = mul i64 [[R3]], [[LSR_IV]] |
| ; CHECK-NEXT: [[R5:%.*]] = add i64 [[R2]], [[R4]] |
| ; CHECK-NEXT: [[R6:%.*]] = icmp ult i64 [[R5]], undef |
| ; CHECK-NEXT: [[R7:%.*]] = getelementptr i64, ptr [[P]], i64 [[R5]] |
| ; CHECK-NEXT: store i64 1, ptr [[R7]], align 8 |
| ; CHECK-NEXT: br label [[L_BACKEDGE]] |
| ; |
| top: |
| br label %L |
| |
| L: ; preds = %idxend.10, %idxend, %L2, %top |
| br i1 %c, label %L, label %L1 |
| |
| L1: ; preds = %L1.preheader, %L2 |
| %r13 = phi i64 [ %r1, %L2 ], [ 1, %L ] |
| %r0 = add i64 %r13, -1 |
| br label %idxend.8 |
| |
| L2: ; preds = %idxend.8 |
| %r1 = add i64 %r13, 1 |
| br i1 %c2, label %L, label %L1 |
| |
| if6: ; preds = %idxend.8 |
| %r2 = add i64 %0, -1 |
| %r3 = load i64, ptr %1, align 8 |
| br label %ib |
| |
| idxend.8: ; preds = %L1 |
| br i1 %c3, label %if6, label %L2 |
| |
| ib: ; preds = %if6 |
| %r4 = mul i64 %r3, %r0 |
| %r5 = add i64 %r2, %r4 |
| %r6 = icmp ult i64 %r5, undef |
| %r7 = getelementptr i64, ptr %p, i64 %r5 |
| store i64 1, ptr %r7, align 8 |
| br label %L |
| } |
