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llvm-project
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llvm
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b72b4128f221fd5086a1ae46aba7b2fcbf0d6384
/
.
/
test
/
MC
/
ARM
/
tMOVSr.s
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@
REQUIRES
:
asserts
@
RUN
:
llvm
-
mc
--
triple
=
thumbv8
--
debug
%s 2>&1 | FileCheck %
s
--
match
-
full
-
lines
@
CHECK
:
Changed to
:
<
MCInst
#{{[0-9]+}} tMOVSr <MCOperand Reg:{{[0-9]+}}> <MCOperand Reg:{{[0-9]+}}>>
.text
movs r2
,
r3