[llvm] Use range-based for loops (NFC)
GitOrigin-RevId: c73fc74ce0f85510ebedd9fe8bcad51d53f2465c
diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp
index a258d81..fc5ac45 100644
--- a/lib/CodeGen/InlineSpiller.cpp
+++ b/lib/CodeGen/InlineSpiller.cpp
@@ -581,11 +581,9 @@
if (!ParentVNI) {
LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
- for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI.getOperand(i);
+ for (MachineOperand &MO : MI.operands())
if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg())
MO.setIsUndef();
- }
LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
return true;
}
diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp
index e183183..cf1f3d0 100644
--- a/lib/CodeGen/MachinePipeliner.cpp
+++ b/lib/CodeGen/MachinePipeliner.cpp
@@ -2546,8 +2546,7 @@
unsigned Pos = 0;
for (std::deque<SUnit *>::iterator I = Insts.begin(), E = Insts.end(); I != E;
++I, ++Pos) {
- for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
+ for (MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
continue;
diff --git a/lib/CodeGen/ModuloSchedule.cpp b/lib/CodeGen/ModuloSchedule.cpp
index e24bb4b..aaa6403 100644
--- a/lib/CodeGen/ModuloSchedule.cpp
+++ b/lib/CodeGen/ModuloSchedule.cpp
@@ -1005,8 +1005,7 @@
unsigned CurStageNum,
unsigned InstrStageNum,
ValueMapTy *VRMap) {
- for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = NewMI->getOperand(i);
+ for (MachineOperand &MO : NewMI->operands()) {
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
continue;
Register reg = MO.getReg();
diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp
index 68920e2..6653145 100644
--- a/lib/CodeGen/RegAllocFast.cpp
+++ b/lib/CodeGen/RegAllocFast.cpp
@@ -1258,8 +1258,7 @@
// Free registers occupied by defs.
// Iterate operands in reverse order, so we see the implicit super register
// defs first (we added them earlier in case of <def,read-undef>).
- for (unsigned I = MI.getNumOperands(); I-- > 0;) {
- MachineOperand &MO = MI.getOperand(I);
+ for (MachineOperand &MO : llvm::reverse(MI.operands())) {
if (!MO.isReg() || !MO.isDef())
continue;
@@ -1362,8 +1361,7 @@
// Free early clobbers.
if (HasEarlyClobber) {
- for (unsigned I = MI.getNumOperands(); I-- > 0; ) {
- MachineOperand &MO = MI.getOperand(I);
+ for (MachineOperand &MO : llvm::reverse(MI.operands())) {
if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber())
continue;
// subreg defs don't free the full register. We left the subreg number
@@ -1440,8 +1438,7 @@
MachineBasicBlock::instr_iterator BundledMI = MI.getIterator();
++BundledMI;
while (BundledMI->isBundledWithPred()) {
- for (unsigned I = 0; I < BundledMI->getNumOperands(); ++I) {
- MachineOperand &MO = BundledMI->getOperand(I);
+ for (MachineOperand &MO : BundledMI->operands()) {
if (!MO.isReg())
continue;
diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp
index 0920e85..f49ba5c 100644
--- a/lib/CodeGen/StackSlotColoring.cpp
+++ b/lib/CodeGen/StackSlotColoring.cpp
@@ -393,8 +393,7 @@
SmallVectorImpl<int> &SlotMapping,
MachineFunction &MF) {
// Update the operands.
- for (unsigned i = 0, ee = MI.getNumOperands(); i != ee; ++i) {
- MachineOperand &MO = MI.getOperand(i);
+ for (MachineOperand &MO : MI.operands()) {
if (!MO.isFI())
continue;
int OldFI = MO.getIndex();
diff --git a/lib/Target/AArch64/AArch64CondBrTuning.cpp b/lib/Target/AArch64/AArch64CondBrTuning.cpp
index a07f564..ff4a4df 100644
--- a/lib/Target/AArch64/AArch64CondBrTuning.cpp
+++ b/lib/Target/AArch64/AArch64CondBrTuning.cpp
@@ -88,12 +88,9 @@
// If this is already the flag setting version of the instruction (e.g., SUBS)
// just make sure the implicit-def of NZCV isn't marked dead.
if (IsFlagSetting) {
- for (unsigned I = MI.getNumExplicitOperands(), E = MI.getNumOperands();
- I != E; ++I) {
- MachineOperand &MO = MI.getOperand(I);
+ for (MachineOperand &MO : MI.implicit_operands())
if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
MO.setIsDead(false);
- }
return &MI;
}
bool Is64Bit;
diff --git a/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index f5adfcf..34c990b 100644
--- a/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6452,8 +6452,7 @@
MachineIRBuilder MIB(MI);
// Go through each operand and ensure it has the same regbank.
- for (unsigned OpIdx = 1; OpIdx < MI.getNumOperands(); ++OpIdx) {
- MachineOperand &MO = MI.getOperand(OpIdx);
+ for (MachineOperand &MO : llvm::drop_begin(MI.operands())) {
if (!MO.isReg())
continue;
Register OpReg = MO.getReg();
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 070066f..fe182ac 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1219,9 +1219,9 @@
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
- for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
- if (UserMI->getOperand(j).isCPI()) {
- UserMI->getOperand(j).setIndex(CPEs[i].CPI);
+ for (MachineOperand &MO : UserMI->operands())
+ if (MO.isCPI()) {
+ MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@@ -1601,9 +1601,9 @@
BBUtils->adjustBBOffsetsAfter(&*--NewIsland->getIterator());
// Finally, change the CPI in the instruction operand to be ID.
- for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
- if (UserMI->getOperand(i).isCPI()) {
- UserMI->getOperand(i).setIndex(ID);
+ for (MachineOperand &MO : UserMI->operands())
+ if (MO.isCPI()) {
+ MO.setIndex(ID);
break;
}
diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index d3bc1b3..03b0f75 100644
--- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -237,12 +237,9 @@
}
static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
- for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
- MachineOperand &Op = MI.getOperand(I);
- if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
- continue;
- Op.setIsKill(false);
- }
+ for (MachineOperand &Op : MI.operands())
+ if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill())
+ Op.setIsKill(false);
}
/// Returns true if it is unsafe to move a copy instruction from \p UseReg to
diff --git a/lib/Target/Mips/MipsConstantIslandPass.cpp b/lib/Target/Mips/MipsConstantIslandPass.cpp
index a95b809..491d379 100644
--- a/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -1066,9 +1066,9 @@
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
- for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
- if (UserMI->getOperand(j).isCPI()) {
- UserMI->getOperand(j).setIndex(CPEs[i].CPI);
+ for (MachineOperand &MO : UserMI->operands())
+ if (MO.isCPI()) {
+ MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@@ -1122,9 +1122,9 @@
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
- for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
- if (UserMI->getOperand(j).isCPI()) {
- UserMI->getOperand(j).setIndex(CPEs[i].CPI);
+ for (MachineOperand &MO : UserMI->operands())
+ if (MO.isCPI()) {
+ MO.setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@@ -1392,9 +1392,9 @@
adjustBBOffsetsAfter(&*--NewIsland->getIterator());
// Finally, change the CPI in the instruction operand to be ID.
- for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
- if (UserMI->getOperand(i).isCPI()) {
- UserMI->getOperand(i).setIndex(ID);
+ for (MachineOperand &MO : UserMI->operands())
+ if (MO.isCPI()) {
+ MO.setIndex(ID);
break;
}
diff --git a/lib/Target/X86/X86ExpandPseudo.cpp b/lib/Target/X86/X86ExpandPseudo.cpp
index 01dc509..93bc230 100644
--- a/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/lib/Target/X86/X86ExpandPseudo.cpp
@@ -209,10 +209,8 @@
llvm_unreachable("unexpected opcode");
OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
- unsigned OpStart = 1;
bool RAXImplicitDead = false;
- for (; OpStart < MI.getNumOperands(); ++OpStart) {
- MachineOperand &Op = MI.getOperand(OpStart);
+ for (MachineOperand &Op : llvm::drop_begin(MI.operands())) {
// RAX may be 'implicit dead', if there are no other users of the return
// value. We introduce a new use, so change it to 'implicit def'.
if (Op.isReg() && Op.isImplicit() && Op.isDead() &&
