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llvm / llvm-project / llvm / b2bdcc05fb17a17e63cbb78e7e1147d647c27877 / . / test / CodeGen / NVPTX / unfold-masked-merge-vector-variablemask.ll
blob: 16579de882ed4b6c73e08c29361798fde800bc17 [file] [log] [blame]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx70 < %s | FileCheck %s
; ============================================================================ ;
; 8-bit vector width
; ============================================================================ ;
define <1 x i8> @out_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
; CHECK-LABEL: out_v1i8(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u8 %rs1, [out_v1i8_param_0];
; CHECK-NEXT: ld.param.u8 %rs2, [out_v1i8_param_2];
; CHECK-NEXT: and.b16 %rs3, %rs1, %rs2;
; CHECK-NEXT: ld.param.u8 %rs4, [out_v1i8_param_1];
; CHECK-NEXT: not.b16 %rs5, %rs2;
; CHECK-NEXT: and.b16 %rs6, %rs4, %rs5;
; CHECK-NEXT: or.b16 %rs7, %rs3, %rs6;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs7;
; CHECK-NEXT: ret;
%mx = and <1 x i8> %x, %mask
%notmask = xor <1 x i8> %mask, <i8 -1>
%my = and <1 x i8> %y, %notmask
%r = or <1 x i8> %mx, %my
ret <1 x i8> %r
}
; ============================================================================ ;
; 16-bit vector width
; ============================================================================ ;
define <1 x i16> @out_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {
; CHECK-LABEL: out_v1i16(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u16 %rs1, [out_v1i16_param_0];
; CHECK-NEXT: ld.param.u16 %rs2, [out_v1i16_param_2];
; CHECK-NEXT: and.b16 %rs3, %rs1, %rs2;
; CHECK-NEXT: ld.param.u16 %rs4, [out_v1i16_param_1];
; CHECK-NEXT: not.b16 %rs5, %rs2;
; CHECK-NEXT: and.b16 %rs6, %rs4, %rs5;
; CHECK-NEXT: or.b16 %rs7, %rs3, %rs6;
; CHECK-NEXT: st.param.b16 [func_retval0+0], %rs7;
; CHECK-NEXT: ret;
%mx = and <1 x i16> %x, %mask
%notmask = xor <1 x i16> %mask, <i16 -1>
%my = and <1 x i16> %y, %notmask
%r = or <1 x i16> %mx, %my
ret <1 x i16> %r
}
; ============================================================================ ;
; 32-bit vector width
; ============================================================================ ;
define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-LABEL: out_v4i8(
; CHECK: {
; CHECK-NEXT: .local .align 2 .b8 __local_depot2[4];
; CHECK-NEXT: .reg .b64 %SP;
; CHECK-NEXT: .reg .b64 %SPL;
; CHECK-NEXT: .reg .b16 %rs<20>;
; CHECK-NEXT: .reg .b32 %r<21>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %SPL, __local_depot2;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [out_v4i8_param_0];
; CHECK-NEXT: mov.b32 %r1, {%rs3, %rs4};
; CHECK-NEXT: mov.b32 %r2, {%rs1, %rs2};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [out_v4i8_param_2];
; CHECK-NEXT: mov.b32 %r3, {%rs5, %rs6};
; CHECK-NEXT: and.b32 %r4, %r2, %r3;
; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
; CHECK-NEXT: and.b32 %r6, %r1, %r5;
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [out_v4i8_param_1];
; CHECK-NEXT: mov.b32 %r7, {%rs11, %rs12};
; CHECK-NEXT: mov.b32 %r8, {%rs9, %rs10};
; CHECK-NEXT: xor.b32 %r9, %r5, 16711935;
; CHECK-NEXT: xor.b32 %r10, %r3, 16711935;
; CHECK-NEXT: and.b32 %r11, %r8, %r10;
; CHECK-NEXT: and.b32 %r12, %r7, %r9;
; CHECK-NEXT: or.b32 %r13, %r6, %r12;
; CHECK-NEXT: mov.b32 {%rs13, %rs14}, %r13;
; CHECK-NEXT: st.v2.u8 [%SP+0], {%rs13, %rs14};
; CHECK-NEXT: or.b32 %r14, %r4, %r11;
; CHECK-NEXT: mov.b32 {%rs15, %rs16}, %r14;
; CHECK-NEXT: st.v2.u8 [%SP+2], {%rs15, %rs16};
; CHECK-NEXT: ld.u16 %r15, [%SP+0];
; CHECK-NEXT: shl.b32 %r16, %r15, 16;
; CHECK-NEXT: ld.u16 %r17, [%SP+2];
; CHECK-NEXT: or.b32 %r18, %r17, %r16;
; CHECK-NEXT: shr.u32 %r19, %r18, 8;
; CHECK-NEXT: cvt.u16.u32 %rs17, %r19;
; CHECK-NEXT: cvt.u16.u32 %rs18, %r15;
; CHECK-NEXT: bfe.s32 %r20, %r15, 8, 8;
; CHECK-NEXT: cvt.u16.u32 %rs19, %r20;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs15, %rs17, %rs18, %rs19};
; CHECK-NEXT: ret;
%mx = and <4 x i8> %x, %mask
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1>
%my = and <4 x i8> %y, %notmask
%r = or <4 x i8> %mx, %my
ret <4 x i8> %r
}
define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-LABEL: out_v4i8_undef(
; CHECK: {
; CHECK-NEXT: .local .align 2 .b8 __local_depot3[4];
; CHECK-NEXT: .reg .b64 %SP;
; CHECK-NEXT: .reg .b64 %SPL;
; CHECK-NEXT: .reg .b16 %rs<22>;
; CHECK-NEXT: .reg .b32 %r<22>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %SPL, __local_depot3;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [out_v4i8_undef_param_0];
; CHECK-NEXT: mov.b32 %r1, {%rs3, %rs4};
; CHECK-NEXT: mov.b32 %r2, {%rs1, %rs2};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [out_v4i8_undef_param_2];
; CHECK-NEXT: mov.b32 %r3, {%rs5, %rs6};
; CHECK-NEXT: and.b32 %r4, %r2, %r3;
; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
; CHECK-NEXT: and.b32 %r6, %r1, %r5;
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [out_v4i8_undef_param_1];
; CHECK-NEXT: mov.b32 %r7, {%rs11, %rs12};
; CHECK-NEXT: mov.b32 %r8, {%rs9, %rs10};
; CHECK-NEXT: mov.u16 %rs13, 255;
; CHECK-NEXT: mov.b32 %r9, {%rs14, %rs13};
; CHECK-NEXT: xor.b32 %r10, %r5, %r9;
; CHECK-NEXT: xor.b32 %r11, %r3, 16711935;
; CHECK-NEXT: and.b32 %r12, %r8, %r11;
; CHECK-NEXT: and.b32 %r13, %r7, %r10;
; CHECK-NEXT: or.b32 %r14, %r6, %r13;
; CHECK-NEXT: mov.b32 {%rs15, %rs16}, %r14;
; CHECK-NEXT: st.v2.u8 [%SP+0], {%rs15, %rs16};
; CHECK-NEXT: or.b32 %r15, %r4, %r12;
; CHECK-NEXT: mov.b32 {%rs17, %rs18}, %r15;
; CHECK-NEXT: st.v2.u8 [%SP+2], {%rs17, %rs18};
; CHECK-NEXT: ld.u16 %r16, [%SP+0];
; CHECK-NEXT: shl.b32 %r17, %r16, 16;
; CHECK-NEXT: ld.u16 %r18, [%SP+2];
; CHECK-NEXT: or.b32 %r19, %r18, %r17;
; CHECK-NEXT: shr.u32 %r20, %r19, 8;
; CHECK-NEXT: cvt.u16.u32 %rs19, %r20;
; CHECK-NEXT: cvt.u16.u32 %rs20, %r16;
; CHECK-NEXT: bfe.s32 %r21, %r16, 8, 8;
; CHECK-NEXT: cvt.u16.u32 %rs21, %r21;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs17, %rs19, %rs20, %rs21};
; CHECK-NEXT: ret;
%mx = and <4 x i8> %x, %mask
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 undef, i8 -1>
%my = and <4 x i8> %y, %notmask
%r = or <4 x i8> %mx, %my
ret <4 x i8> %r
}
define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {
; CHECK-LABEL: out_v2i16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<10>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u32 %r1, [out_v2i16_param_2];
; CHECK-NEXT: ld.param.u32 %r3, [out_v2i16_param_1];
; CHECK-NEXT: ld.param.u32 %r4, [out_v2i16_param_0];
; CHECK-NEXT: and.b32 %r5, %r4, %r1;
; CHECK-NEXT: xor.b32 %r7, %r1, -1;
; CHECK-NEXT: and.b32 %r8, %r3, %r7;
; CHECK-NEXT: or.b32 %r9, %r5, %r8;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r9;
; CHECK-NEXT: ret;
%mx = and <2 x i16> %x, %mask
%notmask = xor <2 x i16> %mask, <i16 -1, i16 -1>
%my = and <2 x i16> %y, %notmask
%r = or <2 x i16> %mx, %my
ret <2 x i16> %r
}
define <1 x i32> @out_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {
; CHECK-LABEL: out_v1i32(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u32 %r1, [out_v1i32_param_0];
; CHECK-NEXT: ld.param.u32 %r2, [out_v1i32_param_2];
; CHECK-NEXT: and.b32 %r3, %r1, %r2;
; CHECK-NEXT: ld.param.u32 %r4, [out_v1i32_param_1];
; CHECK-NEXT: not.b32 %r5, %r2;
; CHECK-NEXT: and.b32 %r6, %r4, %r5;
; CHECK-NEXT: or.b32 %r7, %r3, %r6;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r7;
; CHECK-NEXT: ret;
%mx = and <1 x i32> %x, %mask
%notmask = xor <1 x i32> %mask, <i32 -1>
%my = and <1 x i32> %y, %notmask
%r = or <1 x i32> %mx, %my
ret <1 x i32> %r
}
; ============================================================================ ;
; 64-bit vector width
; ============================================================================ ;
define <8 x i8> @out_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
; CHECK-LABEL: out_v8i8(
; CHECK: {
; CHECK-NEXT: .local .align 2 .b8 __local_depot6[8];
; CHECK-NEXT: .reg .b64 %SP;
; CHECK-NEXT: .reg .b64 %SPL;
; CHECK-NEXT: .reg .b16 %rs<40>;
; CHECK-NEXT: .reg .b32 %r<38>;
; CHECK-NEXT: .reg .b64 %rd<9>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %SPL, __local_depot6;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [out_v8i8_param_0];
; CHECK-NEXT: mov.b32 %r1, {%rs3, %rs4};
; CHECK-NEXT: mov.b32 %r2, {%rs1, %rs2};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [out_v8i8_param_0+4];
; CHECK-NEXT: mov.b32 %r3, {%rs7, %rs8};
; CHECK-NEXT: mov.b32 %r4, {%rs5, %rs6};
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [out_v8i8_param_2+4];
; CHECK-NEXT: mov.b32 %r5, {%rs9, %rs10};
; CHECK-NEXT: and.b32 %r6, %r4, %r5;
; CHECK-NEXT: mov.b32 %r7, {%rs11, %rs12};
; CHECK-NEXT: and.b32 %r8, %r3, %r7;
; CHECK-NEXT: ld.param.v4.u8 {%rs13, %rs14, %rs15, %rs16}, [out_v8i8_param_2];
; CHECK-NEXT: mov.b32 %r9, {%rs13, %rs14};
; CHECK-NEXT: and.b32 %r10, %r2, %r9;
; CHECK-NEXT: mov.b32 %r11, {%rs15, %rs16};
; CHECK-NEXT: and.b32 %r12, %r1, %r11;
; CHECK-NEXT: ld.param.v4.u8 {%rs17, %rs18, %rs19, %rs20}, [out_v8i8_param_1];
; CHECK-NEXT: mov.b32 %r13, {%rs19, %rs20};
; CHECK-NEXT: mov.b32 %r14, {%rs17, %rs18};
; CHECK-NEXT: ld.param.v4.u8 {%rs21, %rs22, %rs23, %rs24}, [out_v8i8_param_1+4];
; CHECK-NEXT: mov.b32 %r15, {%rs23, %rs24};
; CHECK-NEXT: mov.b32 %r16, {%rs21, %rs22};
; CHECK-NEXT: xor.b32 %r17, %r11, 16711935;
; CHECK-NEXT: xor.b32 %r18, %r9, 16711935;
; CHECK-NEXT: xor.b32 %r19, %r7, 16711935;
; CHECK-NEXT: xor.b32 %r20, %r5, 16711935;
; CHECK-NEXT: and.b32 %r21, %r16, %r20;
; CHECK-NEXT: and.b32 %r22, %r15, %r19;
; CHECK-NEXT: and.b32 %r23, %r14, %r18;
; CHECK-NEXT: and.b32 %r24, %r13, %r17;
; CHECK-NEXT: or.b32 %r25, %r12, %r24;
; CHECK-NEXT: mov.b32 {%rs25, %rs26}, %r25;
; CHECK-NEXT: st.v2.u8 [%SP+0], {%rs25, %rs26};
; CHECK-NEXT: or.b32 %r26, %r10, %r23;
; CHECK-NEXT: mov.b32 {%rs27, %rs28}, %r26;
; CHECK-NEXT: st.v2.u8 [%SP+2], {%rs27, %rs28};
; CHECK-NEXT: or.b32 %r27, %r8, %r22;
; CHECK-NEXT: mov.b32 {%rs29, %rs30}, %r27;
; CHECK-NEXT: st.v2.u8 [%SP+4], {%rs29, %rs30};
; CHECK-NEXT: or.b32 %r28, %r6, %r21;
; CHECK-NEXT: mov.b32 {%rs31, %rs32}, %r28;
; CHECK-NEXT: st.v2.u8 [%SP+6], {%rs31, %rs32};
; CHECK-NEXT: ld.u16 %r29, [%SP+0];
; CHECK-NEXT: shl.b32 %r30, %r29, 16;
; CHECK-NEXT: ld.u16 %r31, [%SP+2];
; CHECK-NEXT: or.b32 %r32, %r31, %r30;
; CHECK-NEXT: cvt.u64.u32 %rd1, %r32;
; CHECK-NEXT: ld.u16 %r33, [%SP+4];
; CHECK-NEXT: shl.b32 %r34, %r33, 16;
; CHECK-NEXT: ld.u16 %r35, [%SP+6];
; CHECK-NEXT: or.b32 %r36, %r35, %r34;
; CHECK-NEXT: cvt.u64.u32 %rd2, %r36;
; CHECK-NEXT: shl.b64 %rd3, %rd2, 32;
; CHECK-NEXT: or.b64 %rd4, %rd1, %rd3;
; CHECK-NEXT: shr.u32 %r37, %r36, 8;
; CHECK-NEXT: shr.u64 %rd5, %rd4, 24;
; CHECK-NEXT: cvt.u16.u64 %rs33, %rd5;
; CHECK-NEXT: shr.u64 %rd6, %rd1, 16;
; CHECK-NEXT: cvt.u16.u64 %rs34, %rd6;
; CHECK-NEXT: shr.u64 %rd7, %rd1, 8;
; CHECK-NEXT: cvt.u16.u64 %rs35, %rd7;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs27, %rs35, %rs34, %rs33};
; CHECK-NEXT: cvt.u16.u32 %rs36, %r37;
; CHECK-NEXT: bfe.s64 %rd8, %rd2, 24, 8;
; CHECK-NEXT: cvt.u16.u64 %rs37, %rd8;
; CHECK-NEXT: cvt.u16.u32 %rs38, %r33;
; CHECK-NEXT: cvt.u16.u32 %rs39, %r35;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs39, %rs36, %rs38, %rs37};
; CHECK-NEXT: ret;
%mx = and <8 x i8> %x, %mask
%notmask = xor <8 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%my = and <8 x i8> %y, %notmask
%r = or <8 x i8> %mx, %my
ret <8 x i8> %r
}
define <4 x i16> @out_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
; CHECK-LABEL: out_v4i16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<21>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [out_v4i16_param_1];
; CHECK-NEXT: ld.param.v2.u32 {%r5, %r6}, [out_v4i16_param_2];
; CHECK-NEXT: ld.param.v2.u32 {%r9, %r10}, [out_v4i16_param_0];
; CHECK-NEXT: and.b32 %r11, %r9, %r5;
; CHECK-NEXT: and.b32 %r13, %r10, %r6;
; CHECK-NEXT: xor.b32 %r15, %r6, -1;
; CHECK-NEXT: xor.b32 %r16, %r5, -1;
; CHECK-NEXT: and.b32 %r17, %r1, %r16;
; CHECK-NEXT: and.b32 %r18, %r2, %r15;
; CHECK-NEXT: or.b32 %r19, %r13, %r18;
; CHECK-NEXT: or.b32 %r20, %r11, %r17;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r20, %r19};
; CHECK-NEXT: ret;
%mx = and <4 x i16> %x, %mask
%notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1>
%my = and <4 x i16> %y, %notmask
%r = or <4 x i16> %mx, %my
ret <4 x i16> %r
}
define <4 x i16> @out_v4i16_undef(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
; CHECK-LABEL: out_v4i16_undef(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<22>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [out_v4i16_undef_param_1];
; CHECK-NEXT: ld.param.v2.u32 {%r5, %r6}, [out_v4i16_undef_param_2];
; CHECK-NEXT: ld.param.v2.u32 {%r9, %r10}, [out_v4i16_undef_param_0];
; CHECK-NEXT: and.b32 %r11, %r9, %r5;
; CHECK-NEXT: and.b32 %r13, %r10, %r6;
; CHECK-NEXT: mov.u16 %rs1, -1;
; CHECK-NEXT: mov.b32 %r15, {%rs2, %rs1};
; CHECK-NEXT: xor.b32 %r16, %r6, %r15;
; CHECK-NEXT: xor.b32 %r17, %r5, -1;
; CHECK-NEXT: and.b32 %r18, %r1, %r17;
; CHECK-NEXT: and.b32 %r19, %r2, %r16;
; CHECK-NEXT: or.b32 %r20, %r13, %r19;
; CHECK-NEXT: or.b32 %r21, %r11, %r18;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r21, %r20};
; CHECK-NEXT: ret;
%mx = and <4 x i16> %x, %mask
%notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 undef, i16 -1>
%my = and <4 x i16> %y, %notmask
%r = or <4 x i16> %mx, %my
ret <4 x i16> %r
}
define <2 x i32> @out_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {
; CHECK-LABEL: out_v2i32(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<15>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [out_v2i32_param_0];
; CHECK-NEXT: ld.param.v2.u32 {%r3, %r4}, [out_v2i32_param_2];
; CHECK-NEXT: and.b32 %r5, %r1, %r3;
; CHECK-NEXT: and.b32 %r6, %r2, %r4;
; CHECK-NEXT: ld.param.v2.u32 {%r7, %r8}, [out_v2i32_param_1];
; CHECK-NEXT: not.b32 %r9, %r4;
; CHECK-NEXT: not.b32 %r10, %r3;
; CHECK-NEXT: and.b32 %r11, %r7, %r10;
; CHECK-NEXT: and.b32 %r12, %r8, %r9;
; CHECK-NEXT: or.b32 %r13, %r6, %r12;
; CHECK-NEXT: or.b32 %r14, %r5, %r11;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r14, %r13};
; CHECK-NEXT: ret;
%mx = and <2 x i32> %x, %mask
%notmask = xor <2 x i32> %mask, <i32 -1, i32 -1>
%my = and <2 x i32> %y, %notmask
%r = or <2 x i32> %mx, %my
ret <2 x i32> %r
}
define <1 x i64> @out_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {
; CHECK-LABEL: out_v1i64(
; CHECK: {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u64 %rd1, [out_v1i64_param_0];
; CHECK-NEXT: ld.param.u64 %rd2, [out_v1i64_param_2];
; CHECK-NEXT: and.b64 %rd3, %rd1, %rd2;
; CHECK-NEXT: ld.param.u64 %rd4, [out_v1i64_param_1];
; CHECK-NEXT: not.b64 %rd5, %rd2;
; CHECK-NEXT: and.b64 %rd6, %rd4, %rd5;
; CHECK-NEXT: or.b64 %rd7, %rd3, %rd6;
; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd7;
; CHECK-NEXT: ret;
%mx = and <1 x i64> %x, %mask
%notmask = xor <1 x i64> %mask, <i64 -1>
%my = and <1 x i64> %y, %notmask
%r = or <1 x i64> %mx, %my
ret <1 x i64> %r
}
; ============================================================================ ;
; 128-bit vector width
; ============================================================================ ;
define <16 x i8> @out_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {
; CHECK-LABEL: out_v16i8(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<65>;
; CHECK-NEXT: .reg .b32 %r<57>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [out_v16i8_param_0+12];
; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
; CHECK-NEXT: mov.b32 %r2, {%rs3, %rs4};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [out_v16i8_param_0+8];
; CHECK-NEXT: mov.b32 %r3, {%rs5, %rs6};
; CHECK-NEXT: mov.b32 %r4, {%rs7, %rs8};
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [out_v16i8_param_0+4];
; CHECK-NEXT: mov.b32 %r5, {%rs9, %rs10};
; CHECK-NEXT: mov.b32 %r6, {%rs11, %rs12};
; CHECK-NEXT: ld.param.v4.u8 {%rs13, %rs14, %rs15, %rs16}, [out_v16i8_param_0];
; CHECK-NEXT: mov.b32 %r7, {%rs13, %rs14};
; CHECK-NEXT: mov.b32 %r8, {%rs15, %rs16};
; CHECK-NEXT: ld.param.v4.u8 {%rs17, %rs18, %rs19, %rs20}, [out_v16i8_param_2];
; CHECK-NEXT: mov.b32 %r9, {%rs19, %rs20};
; CHECK-NEXT: and.b32 %r10, %r8, %r9;
; CHECK-NEXT: mov.b32 %r11, {%rs17, %rs18};
; CHECK-NEXT: and.b32 %r12, %r7, %r11;
; CHECK-NEXT: ld.param.v4.u8 {%rs21, %rs22, %rs23, %rs24}, [out_v16i8_param_2+4];
; CHECK-NEXT: mov.b32 %r13, {%rs23, %rs24};
; CHECK-NEXT: and.b32 %r14, %r6, %r13;
; CHECK-NEXT: mov.b32 %r15, {%rs21, %rs22};
; CHECK-NEXT: and.b32 %r16, %r5, %r15;
; CHECK-NEXT: ld.param.v4.u8 {%rs25, %rs26, %rs27, %rs28}, [out_v16i8_param_2+8];
; CHECK-NEXT: mov.b32 %r17, {%rs27, %rs28};
; CHECK-NEXT: and.b32 %r18, %r4, %r17;
; CHECK-NEXT: mov.b32 %r19, {%rs25, %rs26};
; CHECK-NEXT: and.b32 %r20, %r3, %r19;
; CHECK-NEXT: ld.param.v4.u8 {%rs29, %rs30, %rs31, %rs32}, [out_v16i8_param_2+12];
; CHECK-NEXT: mov.b32 %r21, {%rs31, %rs32};
; CHECK-NEXT: and.b32 %r22, %r2, %r21;
; CHECK-NEXT: mov.b32 %r23, {%rs29, %rs30};
; CHECK-NEXT: and.b32 %r24, %r1, %r23;
; CHECK-NEXT: ld.param.v4.u8 {%rs33, %rs34, %rs35, %rs36}, [out_v16i8_param_1+12];
; CHECK-NEXT: mov.b32 %r25, {%rs33, %rs34};
; CHECK-NEXT: mov.b32 %r26, {%rs35, %rs36};
; CHECK-NEXT: ld.param.v4.u8 {%rs37, %rs38, %rs39, %rs40}, [out_v16i8_param_1+8];
; CHECK-NEXT: mov.b32 %r27, {%rs37, %rs38};
; CHECK-NEXT: mov.b32 %r28, {%rs39, %rs40};
; CHECK-NEXT: ld.param.v4.u8 {%rs41, %rs42, %rs43, %rs44}, [out_v16i8_param_1+4];
; CHECK-NEXT: mov.b32 %r29, {%rs41, %rs42};
; CHECK-NEXT: mov.b32 %r30, {%rs43, %rs44};
; CHECK-NEXT: ld.param.v4.u8 {%rs45, %rs46, %rs47, %rs48}, [out_v16i8_param_1];
; CHECK-NEXT: mov.b32 %r31, {%rs45, %rs46};
; CHECK-NEXT: mov.b32 %r32, {%rs47, %rs48};
; CHECK-NEXT: xor.b32 %r33, %r23, 16711935;
; CHECK-NEXT: xor.b32 %r34, %r21, 16711935;
; CHECK-NEXT: xor.b32 %r35, %r19, 16711935;
; CHECK-NEXT: xor.b32 %r36, %r17, 16711935;
; CHECK-NEXT: xor.b32 %r37, %r15, 16711935;
; CHECK-NEXT: xor.b32 %r38, %r13, 16711935;
; CHECK-NEXT: xor.b32 %r39, %r11, 16711935;
; CHECK-NEXT: xor.b32 %r40, %r9, 16711935;
; CHECK-NEXT: and.b32 %r41, %r32, %r40;
; CHECK-NEXT: and.b32 %r42, %r31, %r39;
; CHECK-NEXT: and.b32 %r43, %r30, %r38;
; CHECK-NEXT: and.b32 %r44, %r29, %r37;
; CHECK-NEXT: and.b32 %r45, %r28, %r36;
; CHECK-NEXT: and.b32 %r46, %r27, %r35;
; CHECK-NEXT: and.b32 %r47, %r26, %r34;
; CHECK-NEXT: and.b32 %r48, %r25, %r33;
; CHECK-NEXT: or.b32 %r49, %r24, %r48;
; CHECK-NEXT: or.b32 %r50, %r22, %r47;
; CHECK-NEXT: or.b32 %r51, %r20, %r46;
; CHECK-NEXT: or.b32 %r52, %r18, %r45;
; CHECK-NEXT: or.b32 %r53, %r16, %r44;
; CHECK-NEXT: or.b32 %r54, %r14, %r43;
; CHECK-NEXT: or.b32 %r55, %r12, %r42;
; CHECK-NEXT: or.b32 %r56, %r10, %r41;
; CHECK-NEXT: mov.b32 {%rs49, %rs50}, %r56;
; CHECK-NEXT: mov.b32 {%rs51, %rs52}, %r55;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs51, %rs52, %rs49, %rs50};
; CHECK-NEXT: mov.b32 {%rs53, %rs54}, %r54;
; CHECK-NEXT: mov.b32 {%rs55, %rs56}, %r53;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs55, %rs56, %rs53, %rs54};
; CHECK-NEXT: mov.b32 {%rs57, %rs58}, %r52;
; CHECK-NEXT: mov.b32 {%rs59, %rs60}, %r51;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs59, %rs60, %rs57, %rs58};
; CHECK-NEXT: mov.b32 {%rs61, %rs62}, %r50;
; CHECK-NEXT: mov.b32 {%rs63, %rs64}, %r49;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+12], {%rs63, %rs64, %rs61, %rs62};
; CHECK-NEXT: ret;
%mx = and <16 x i8> %x, %mask
%notmask = xor <16 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%my = and <16 x i8> %y, %notmask
%r = or <16 x i8> %mx, %my
ret <16 x i8> %r
}
define <8 x i16> @out_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {
; CHECK-LABEL: out_v8i16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<41>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [out_v8i16_param_1];
; CHECK-NEXT: ld.param.v4.u32 {%r9, %r10, %r11, %r12}, [out_v8i16_param_2];
; CHECK-NEXT: ld.param.v4.u32 {%r17, %r18, %r19, %r20}, [out_v8i16_param_0];
; CHECK-NEXT: and.b32 %r21, %r17, %r9;
; CHECK-NEXT: and.b32 %r23, %r18, %r10;
; CHECK-NEXT: and.b32 %r25, %r19, %r11;
; CHECK-NEXT: and.b32 %r27, %r20, %r12;
; CHECK-NEXT: xor.b32 %r29, %r12, -1;
; CHECK-NEXT: xor.b32 %r30, %r11, -1;
; CHECK-NEXT: xor.b32 %r31, %r10, -1;
; CHECK-NEXT: xor.b32 %r32, %r9, -1;
; CHECK-NEXT: and.b32 %r33, %r1, %r32;
; CHECK-NEXT: and.b32 %r34, %r2, %r31;
; CHECK-NEXT: and.b32 %r35, %r3, %r30;
; CHECK-NEXT: and.b32 %r36, %r4, %r29;
; CHECK-NEXT: or.b32 %r37, %r27, %r36;
; CHECK-NEXT: or.b32 %r38, %r25, %r35;
; CHECK-NEXT: or.b32 %r39, %r23, %r34;
; CHECK-NEXT: or.b32 %r40, %r21, %r33;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r40, %r39, %r38, %r37};
; CHECK-NEXT: ret;
%mx = and <8 x i16> %x, %mask
%notmask = xor <8 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%my = and <8 x i16> %y, %notmask
%r = or <8 x i16> %mx, %my
ret <8 x i16> %r
}
define <4 x i32> @out_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
; CHECK-LABEL: out_v4i32(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<29>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [out_v4i32_param_0];
; CHECK-NEXT: ld.param.v4.u32 {%r5, %r6, %r7, %r8}, [out_v4i32_param_2];
; CHECK-NEXT: and.b32 %r9, %r1, %r5;
; CHECK-NEXT: and.b32 %r10, %r2, %r6;
; CHECK-NEXT: and.b32 %r11, %r3, %r7;
; CHECK-NEXT: and.b32 %r12, %r4, %r8;
; CHECK-NEXT: ld.param.v4.u32 {%r13, %r14, %r15, %r16}, [out_v4i32_param_1];
; CHECK-NEXT: not.b32 %r17, %r8;
; CHECK-NEXT: not.b32 %r18, %r7;
; CHECK-NEXT: not.b32 %r19, %r6;
; CHECK-NEXT: not.b32 %r20, %r5;
; CHECK-NEXT: and.b32 %r21, %r13, %r20;
; CHECK-NEXT: and.b32 %r22, %r14, %r19;
; CHECK-NEXT: and.b32 %r23, %r15, %r18;
; CHECK-NEXT: and.b32 %r24, %r16, %r17;
; CHECK-NEXT: or.b32 %r25, %r12, %r24;
; CHECK-NEXT: or.b32 %r26, %r11, %r23;
; CHECK-NEXT: or.b32 %r27, %r10, %r22;
; CHECK-NEXT: or.b32 %r28, %r9, %r21;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r28, %r27, %r26, %r25};
; CHECK-NEXT: ret;
%mx = and <4 x i32> %x, %mask
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
%my = and <4 x i32> %y, %notmask
%r = or <4 x i32> %mx, %my
ret <4 x i32> %r
}
define <4 x i32> @out_v4i32_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
; CHECK-LABEL: out_v4i32_undef(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<26>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [out_v4i32_undef_param_0];
; CHECK-NEXT: ld.param.v4.u32 {%r5, %r6, %r7, %r8}, [out_v4i32_undef_param_2];
; CHECK-NEXT: and.b32 %r9, %r3, %r7;
; CHECK-NEXT: and.b32 %r10, %r1, %r5;
; CHECK-NEXT: and.b32 %r11, %r2, %r6;
; CHECK-NEXT: and.b32 %r12, %r4, %r8;
; CHECK-NEXT: ld.param.v4.u32 {%r13, %r14, %r15, %r16}, [out_v4i32_undef_param_1];
; CHECK-NEXT: not.b32 %r17, %r8;
; CHECK-NEXT: not.b32 %r18, %r6;
; CHECK-NEXT: not.b32 %r19, %r5;
; CHECK-NEXT: and.b32 %r20, %r13, %r19;
; CHECK-NEXT: and.b32 %r21, %r14, %r18;
; CHECK-NEXT: and.b32 %r22, %r16, %r17;
; CHECK-NEXT: or.b32 %r23, %r12, %r22;
; CHECK-NEXT: or.b32 %r24, %r11, %r21;
; CHECK-NEXT: or.b32 %r25, %r10, %r20;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r25, %r24, %r9, %r23};
; CHECK-NEXT: ret;
%mx = and <4 x i32> %x, %mask
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 undef, i32 -1>
%my = and <4 x i32> %y, %notmask
%r = or <4 x i32> %mx, %my
ret <4 x i32> %r
}
define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {
; CHECK-LABEL: out_v2i64(
; CHECK: {
; CHECK-NEXT: .reg .b64 %rd<15>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u64 {%rd1, %rd2}, [out_v2i64_param_0];
; CHECK-NEXT: ld.param.v2.u64 {%rd3, %rd4}, [out_v2i64_param_2];
; CHECK-NEXT: and.b64 %rd5, %rd1, %rd3;
; CHECK-NEXT: and.b64 %rd6, %rd2, %rd4;
; CHECK-NEXT: ld.param.v2.u64 {%rd7, %rd8}, [out_v2i64_param_1];
; CHECK-NEXT: not.b64 %rd9, %rd4;
; CHECK-NEXT: not.b64 %rd10, %rd3;
; CHECK-NEXT: and.b64 %rd11, %rd7, %rd10;
; CHECK-NEXT: and.b64 %rd12, %rd8, %rd9;
; CHECK-NEXT: or.b64 %rd13, %rd6, %rd12;
; CHECK-NEXT: or.b64 %rd14, %rd5, %rd11;
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd14, %rd13};
; CHECK-NEXT: ret;
%mx = and <2 x i64> %x, %mask
%notmask = xor <2 x i64> %mask, <i64 -1, i64 -1>
%my = and <2 x i64> %y, %notmask
%r = or <2 x i64> %mx, %my
ret <2 x i64> %r
}
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Should be the same as the previous one.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ============================================================================ ;
; 8-bit vector width
; ============================================================================ ;
define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
; CHECK-LABEL: in_v1i8(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u8 %rs1, [in_v1i8_param_0];
; CHECK-NEXT: ld.param.u8 %rs2, [in_v1i8_param_1];
; CHECK-NEXT: xor.b16 %rs3, %rs1, %rs2;
; CHECK-NEXT: ld.param.u8 %rs4, [in_v1i8_param_2];
; CHECK-NEXT: and.b16 %rs5, %rs3, %rs4;
; CHECK-NEXT: xor.b16 %rs6, %rs5, %rs2;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i8> %x, %y
%n1 = and <1 x i8> %n0, %mask
%r = xor <1 x i8> %n1, %y
ret <1 x i8> %r
}
; ============================================================================ ;
; 16-bit vector width
; ============================================================================ ;
define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {
; CHECK-LABEL: in_v1i16(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u16 %rs1, [in_v1i16_param_0];
; CHECK-NEXT: ld.param.u16 %rs2, [in_v1i16_param_1];
; CHECK-NEXT: xor.b16 %rs3, %rs1, %rs2;
; CHECK-NEXT: ld.param.u16 %rs4, [in_v1i16_param_2];
; CHECK-NEXT: and.b16 %rs5, %rs3, %rs4;
; CHECK-NEXT: xor.b16 %rs6, %rs5, %rs2;
; CHECK-NEXT: st.param.b16 [func_retval0+0], %rs6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i16> %x, %y
%n1 = and <1 x i16> %n0, %mask
%r = xor <1 x i16> %n1, %y
ret <1 x i16> %r
}
; ============================================================================ ;
; 32-bit vector width
; ============================================================================ ;
define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-LABEL: in_v4i8(
; CHECK: {
; CHECK-NEXT: .local .align 2 .b8 __local_depot18[4];
; CHECK-NEXT: .reg .b64 %SP;
; CHECK-NEXT: .reg .b64 %SPL;
; CHECK-NEXT: .reg .b16 %rs<20>;
; CHECK-NEXT: .reg .b32 %r<19>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %SPL, __local_depot18;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [in_v4i8_param_0];
; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
; CHECK-NEXT: mov.b32 %r2, {%rs3, %rs4};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [in_v4i8_param_1];
; CHECK-NEXT: mov.b32 %r3, {%rs7, %rs8};
; CHECK-NEXT: xor.b32 %r4, %r2, %r3;
; CHECK-NEXT: mov.b32 %r5, {%rs5, %rs6};
; CHECK-NEXT: xor.b32 %r6, %r1, %r5;
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [in_v4i8_param_2];
; CHECK-NEXT: mov.b32 %r7, {%rs9, %rs10};
; CHECK-NEXT: and.b32 %r8, %r6, %r7;
; CHECK-NEXT: mov.b32 %r9, {%rs11, %rs12};
; CHECK-NEXT: and.b32 %r10, %r4, %r9;
; CHECK-NEXT: xor.b32 %r11, %r10, %r3;
; CHECK-NEXT: mov.b32 {%rs13, %rs14}, %r11;
; CHECK-NEXT: st.v2.u8 [%SP+0], {%rs13, %rs14};
; CHECK-NEXT: xor.b32 %r12, %r8, %r5;
; CHECK-NEXT: mov.b32 {%rs15, %rs16}, %r12;
; CHECK-NEXT: st.v2.u8 [%SP+2], {%rs15, %rs16};
; CHECK-NEXT: ld.u16 %r13, [%SP+0];
; CHECK-NEXT: shl.b32 %r14, %r13, 16;
; CHECK-NEXT: ld.u16 %r15, [%SP+2];
; CHECK-NEXT: or.b32 %r16, %r15, %r14;
; CHECK-NEXT: shr.u32 %r17, %r16, 8;
; CHECK-NEXT: cvt.u16.u32 %rs17, %r17;
; CHECK-NEXT: cvt.u16.u32 %rs18, %r13;
; CHECK-NEXT: bfe.s32 %r18, %r13, 8, 8;
; CHECK-NEXT: cvt.u16.u32 %rs19, %r18;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs15, %rs17, %rs18, %rs19};
; CHECK-NEXT: ret;
%n0 = xor <4 x i8> %x, %y
%n1 = and <4 x i8> %n0, %mask
%r = xor <4 x i8> %n1, %y
ret <4 x i8> %r
}
define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {
; CHECK-LABEL: in_v2i16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u32 %r1, [in_v2i16_param_0];
; CHECK-NEXT: ld.param.u32 %r2, [in_v2i16_param_1];
; CHECK-NEXT: xor.b32 %r3, %r1, %r2;
; CHECK-NEXT: ld.param.u32 %r4, [in_v2i16_param_2];
; CHECK-NEXT: and.b32 %r5, %r3, %r4;
; CHECK-NEXT: xor.b32 %r6, %r5, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r6;
; CHECK-NEXT: ret;
%n0 = xor <2 x i16> %x, %y
%n1 = and <2 x i16> %n0, %mask
%r = xor <2 x i16> %n1, %y
ret <2 x i16> %r
}
define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {
; CHECK-LABEL: in_v1i32(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u32 %r1, [in_v1i32_param_0];
; CHECK-NEXT: ld.param.u32 %r2, [in_v1i32_param_1];
; CHECK-NEXT: xor.b32 %r3, %r1, %r2;
; CHECK-NEXT: ld.param.u32 %r4, [in_v1i32_param_2];
; CHECK-NEXT: and.b32 %r5, %r3, %r4;
; CHECK-NEXT: xor.b32 %r6, %r5, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i32> %x, %y
%n1 = and <1 x i32> %n0, %mask
%r = xor <1 x i32> %n1, %y
ret <1 x i32> %r
}
; ============================================================================ ;
; 64-bit vector width
; ============================================================================ ;
define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
; CHECK-LABEL: in_v8i8(
; CHECK: {
; CHECK-NEXT: .local .align 2 .b8 __local_depot21[8];
; CHECK-NEXT: .reg .b64 %SP;
; CHECK-NEXT: .reg .b64 %SPL;
; CHECK-NEXT: .reg .b16 %rs<40>;
; CHECK-NEXT: .reg .b32 %r<34>;
; CHECK-NEXT: .reg .b64 %rd<9>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %SPL, __local_depot21;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [in_v8i8_param_0+4];
; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
; CHECK-NEXT: mov.b32 %r2, {%rs3, %rs4};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [in_v8i8_param_0];
; CHECK-NEXT: mov.b32 %r3, {%rs5, %rs6};
; CHECK-NEXT: mov.b32 %r4, {%rs7, %rs8};
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [in_v8i8_param_1];
; CHECK-NEXT: mov.b32 %r5, {%rs11, %rs12};
; CHECK-NEXT: xor.b32 %r6, %r4, %r5;
; CHECK-NEXT: mov.b32 %r7, {%rs9, %rs10};
; CHECK-NEXT: xor.b32 %r8, %r3, %r7;
; CHECK-NEXT: ld.param.v4.u8 {%rs13, %rs14, %rs15, %rs16}, [in_v8i8_param_1+4];
; CHECK-NEXT: mov.b32 %r9, {%rs15, %rs16};
; CHECK-NEXT: xor.b32 %r10, %r2, %r9;
; CHECK-NEXT: mov.b32 %r11, {%rs13, %rs14};
; CHECK-NEXT: xor.b32 %r12, %r1, %r11;
; CHECK-NEXT: ld.param.v4.u8 {%rs17, %rs18, %rs19, %rs20}, [in_v8i8_param_2+4];
; CHECK-NEXT: mov.b32 %r13, {%rs17, %rs18};
; CHECK-NEXT: and.b32 %r14, %r12, %r13;
; CHECK-NEXT: mov.b32 %r15, {%rs19, %rs20};
; CHECK-NEXT: and.b32 %r16, %r10, %r15;
; CHECK-NEXT: ld.param.v4.u8 {%rs21, %rs22, %rs23, %rs24}, [in_v8i8_param_2];
; CHECK-NEXT: mov.b32 %r17, {%rs21, %rs22};
; CHECK-NEXT: and.b32 %r18, %r8, %r17;
; CHECK-NEXT: mov.b32 %r19, {%rs23, %rs24};
; CHECK-NEXT: and.b32 %r20, %r6, %r19;
; CHECK-NEXT: xor.b32 %r21, %r20, %r5;
; CHECK-NEXT: mov.b32 {%rs25, %rs26}, %r21;
; CHECK-NEXT: st.v2.u8 [%SP+0], {%rs25, %rs26};
; CHECK-NEXT: xor.b32 %r22, %r18, %r7;
; CHECK-NEXT: mov.b32 {%rs27, %rs28}, %r22;
; CHECK-NEXT: st.v2.u8 [%SP+2], {%rs27, %rs28};
; CHECK-NEXT: xor.b32 %r23, %r16, %r9;
; CHECK-NEXT: mov.b32 {%rs29, %rs30}, %r23;
; CHECK-NEXT: st.v2.u8 [%SP+4], {%rs29, %rs30};
; CHECK-NEXT: xor.b32 %r24, %r14, %r11;
; CHECK-NEXT: mov.b32 {%rs31, %rs32}, %r24;
; CHECK-NEXT: st.v2.u8 [%SP+6], {%rs31, %rs32};
; CHECK-NEXT: ld.u16 %r25, [%SP+0];
; CHECK-NEXT: shl.b32 %r26, %r25, 16;
; CHECK-NEXT: ld.u16 %r27, [%SP+2];
; CHECK-NEXT: or.b32 %r28, %r27, %r26;
; CHECK-NEXT: cvt.u64.u32 %rd1, %r28;
; CHECK-NEXT: ld.u16 %r29, [%SP+4];
; CHECK-NEXT: shl.b32 %r30, %r29, 16;
; CHECK-NEXT: ld.u16 %r31, [%SP+6];
; CHECK-NEXT: or.b32 %r32, %r31, %r30;
; CHECK-NEXT: cvt.u64.u32 %rd2, %r32;
; CHECK-NEXT: shl.b64 %rd3, %rd2, 32;
; CHECK-NEXT: or.b64 %rd4, %rd1, %rd3;
; CHECK-NEXT: shr.u32 %r33, %r32, 8;
; CHECK-NEXT: shr.u64 %rd5, %rd4, 24;
; CHECK-NEXT: cvt.u16.u64 %rs33, %rd5;
; CHECK-NEXT: shr.u64 %rd6, %rd1, 16;
; CHECK-NEXT: cvt.u16.u64 %rs34, %rd6;
; CHECK-NEXT: shr.u64 %rd7, %rd1, 8;
; CHECK-NEXT: cvt.u16.u64 %rs35, %rd7;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs27, %rs35, %rs34, %rs33};
; CHECK-NEXT: cvt.u16.u32 %rs36, %r33;
; CHECK-NEXT: bfe.s64 %rd8, %rd2, 24, 8;
; CHECK-NEXT: cvt.u16.u64 %rs37, %rd8;
; CHECK-NEXT: cvt.u16.u32 %rs38, %r29;
; CHECK-NEXT: cvt.u16.u32 %rs39, %r31;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs39, %rs36, %rs38, %rs37};
; CHECK-NEXT: ret;
%n0 = xor <8 x i8> %x, %y
%n1 = and <8 x i8> %n0, %mask
%r = xor <8 x i8> %n1, %y
ret <8 x i8> %r
}
define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
; CHECK-LABEL: in_v4i16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<15>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [in_v4i16_param_0];
; CHECK-NEXT: ld.param.v2.u32 {%r3, %r4}, [in_v4i16_param_1];
; CHECK-NEXT: ld.param.v2.u32 {%r5, %r6}, [in_v4i16_param_2];
; CHECK-NEXT: xor.b32 %r7, %r2, %r4;
; CHECK-NEXT: and.b32 %r8, %r7, %r6;
; CHECK-NEXT: xor.b32 %r9, %r8, %r4;
; CHECK-NEXT: xor.b32 %r11, %r1, %r3;
; CHECK-NEXT: and.b32 %r12, %r11, %r5;
; CHECK-NEXT: xor.b32 %r13, %r12, %r3;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r13, %r9};
; CHECK-NEXT: ret;
%n0 = xor <4 x i16> %x, %y
%n1 = and <4 x i16> %n0, %mask
%r = xor <4 x i16> %n1, %y
ret <4 x i16> %r
}
define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {
; CHECK-LABEL: in_v2i32(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<13>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [in_v2i32_param_0];
; CHECK-NEXT: ld.param.v2.u32 {%r3, %r4}, [in_v2i32_param_1];
; CHECK-NEXT: xor.b32 %r5, %r2, %r4;
; CHECK-NEXT: xor.b32 %r6, %r1, %r3;
; CHECK-NEXT: ld.param.v2.u32 {%r7, %r8}, [in_v2i32_param_2];
; CHECK-NEXT: and.b32 %r9, %r6, %r7;
; CHECK-NEXT: and.b32 %r10, %r5, %r8;
; CHECK-NEXT: xor.b32 %r11, %r10, %r4;
; CHECK-NEXT: xor.b32 %r12, %r9, %r3;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r12, %r11};
; CHECK-NEXT: ret;
%n0 = xor <2 x i32> %x, %y
%n1 = and <2 x i32> %n0, %mask
%r = xor <2 x i32> %n1, %y
ret <2 x i32> %r
}
define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {
; CHECK-LABEL: in_v1i64(
; CHECK: {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.u64 %rd1, [in_v1i64_param_0];
; CHECK-NEXT: ld.param.u64 %rd2, [in_v1i64_param_1];
; CHECK-NEXT: xor.b64 %rd3, %rd1, %rd2;
; CHECK-NEXT: ld.param.u64 %rd4, [in_v1i64_param_2];
; CHECK-NEXT: and.b64 %rd5, %rd3, %rd4;
; CHECK-NEXT: xor.b64 %rd6, %rd5, %rd2;
; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i64> %x, %y
%n1 = and <1 x i64> %n0, %mask
%r = xor <1 x i64> %n1, %y
ret <1 x i64> %r
}
; ============================================================================ ;
; 128-bit vector width
; ============================================================================ ;
define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {
; CHECK-LABEL: in_v16i8(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<65>;
; CHECK-NEXT: .reg .b32 %r<49>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u8 {%rs1, %rs2, %rs3, %rs4}, [in_v16i8_param_0];
; CHECK-NEXT: mov.b32 %r1, {%rs3, %rs4};
; CHECK-NEXT: mov.b32 %r2, {%rs1, %rs2};
; CHECK-NEXT: ld.param.v4.u8 {%rs5, %rs6, %rs7, %rs8}, [in_v16i8_param_0+4];
; CHECK-NEXT: mov.b32 %r3, {%rs7, %rs8};
; CHECK-NEXT: mov.b32 %r4, {%rs5, %rs6};
; CHECK-NEXT: ld.param.v4.u8 {%rs9, %rs10, %rs11, %rs12}, [in_v16i8_param_0+8];
; CHECK-NEXT: mov.b32 %r5, {%rs11, %rs12};
; CHECK-NEXT: mov.b32 %r6, {%rs9, %rs10};
; CHECK-NEXT: ld.param.v4.u8 {%rs13, %rs14, %rs15, %rs16}, [in_v16i8_param_0+12];
; CHECK-NEXT: mov.b32 %r7, {%rs15, %rs16};
; CHECK-NEXT: mov.b32 %r8, {%rs13, %rs14};
; CHECK-NEXT: ld.param.v4.u8 {%rs17, %rs18, %rs19, %rs20}, [in_v16i8_param_1+12];
; CHECK-NEXT: mov.b32 %r9, {%rs17, %rs18};
; CHECK-NEXT: xor.b32 %r10, %r8, %r9;
; CHECK-NEXT: mov.b32 %r11, {%rs19, %rs20};
; CHECK-NEXT: xor.b32 %r12, %r7, %r11;
; CHECK-NEXT: ld.param.v4.u8 {%rs21, %rs22, %rs23, %rs24}, [in_v16i8_param_1+8];
; CHECK-NEXT: mov.b32 %r13, {%rs21, %rs22};
; CHECK-NEXT: xor.b32 %r14, %r6, %r13;
; CHECK-NEXT: mov.b32 %r15, {%rs23, %rs24};
; CHECK-NEXT: xor.b32 %r16, %r5, %r15;
; CHECK-NEXT: ld.param.v4.u8 {%rs25, %rs26, %rs27, %rs28}, [in_v16i8_param_1+4];
; CHECK-NEXT: mov.b32 %r17, {%rs25, %rs26};
; CHECK-NEXT: xor.b32 %r18, %r4, %r17;
; CHECK-NEXT: mov.b32 %r19, {%rs27, %rs28};
; CHECK-NEXT: xor.b32 %r20, %r3, %r19;
; CHECK-NEXT: ld.param.v4.u8 {%rs29, %rs30, %rs31, %rs32}, [in_v16i8_param_1];
; CHECK-NEXT: mov.b32 %r21, {%rs29, %rs30};
; CHECK-NEXT: xor.b32 %r22, %r2, %r21;
; CHECK-NEXT: mov.b32 %r23, {%rs31, %rs32};
; CHECK-NEXT: xor.b32 %r24, %r1, %r23;
; CHECK-NEXT: ld.param.v4.u8 {%rs33, %rs34, %rs35, %rs36}, [in_v16i8_param_2];
; CHECK-NEXT: mov.b32 %r25, {%rs35, %rs36};
; CHECK-NEXT: and.b32 %r26, %r24, %r25;
; CHECK-NEXT: mov.b32 %r27, {%rs33, %rs34};
; CHECK-NEXT: and.b32 %r28, %r22, %r27;
; CHECK-NEXT: ld.param.v4.u8 {%rs37, %rs38, %rs39, %rs40}, [in_v16i8_param_2+4];
; CHECK-NEXT: mov.b32 %r29, {%rs39, %rs40};
; CHECK-NEXT: and.b32 %r30, %r20, %r29;
; CHECK-NEXT: mov.b32 %r31, {%rs37, %rs38};
; CHECK-NEXT: and.b32 %r32, %r18, %r31;
; CHECK-NEXT: ld.param.v4.u8 {%rs41, %rs42, %rs43, %rs44}, [in_v16i8_param_2+8];
; CHECK-NEXT: mov.b32 %r33, {%rs43, %rs44};
; CHECK-NEXT: and.b32 %r34, %r16, %r33;
; CHECK-NEXT: mov.b32 %r35, {%rs41, %rs42};
; CHECK-NEXT: and.b32 %r36, %r14, %r35;
; CHECK-NEXT: ld.param.v4.u8 {%rs45, %rs46, %rs47, %rs48}, [in_v16i8_param_2+12];
; CHECK-NEXT: mov.b32 %r37, {%rs47, %rs48};
; CHECK-NEXT: and.b32 %r38, %r12, %r37;
; CHECK-NEXT: mov.b32 %r39, {%rs45, %rs46};
; CHECK-NEXT: and.b32 %r40, %r10, %r39;
; CHECK-NEXT: xor.b32 %r41, %r40, %r9;
; CHECK-NEXT: xor.b32 %r42, %r38, %r11;
; CHECK-NEXT: xor.b32 %r43, %r36, %r13;
; CHECK-NEXT: xor.b32 %r44, %r34, %r15;
; CHECK-NEXT: xor.b32 %r45, %r32, %r17;
; CHECK-NEXT: xor.b32 %r46, %r30, %r19;
; CHECK-NEXT: xor.b32 %r47, %r28, %r21;
; CHECK-NEXT: xor.b32 %r48, %r26, %r23;
; CHECK-NEXT: mov.b32 {%rs49, %rs50}, %r48;
; CHECK-NEXT: mov.b32 {%rs51, %rs52}, %r47;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs51, %rs52, %rs49, %rs50};
; CHECK-NEXT: mov.b32 {%rs53, %rs54}, %r46;
; CHECK-NEXT: mov.b32 {%rs55, %rs56}, %r45;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs55, %rs56, %rs53, %rs54};
; CHECK-NEXT: mov.b32 {%rs57, %rs58}, %r44;
; CHECK-NEXT: mov.b32 {%rs59, %rs60}, %r43;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs59, %rs60, %rs57, %rs58};
; CHECK-NEXT: mov.b32 {%rs61, %rs62}, %r42;
; CHECK-NEXT: mov.b32 {%rs63, %rs64}, %r41;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+12], {%rs63, %rs64, %rs61, %rs62};
; CHECK-NEXT: ret;
%n0 = xor <16 x i8> %x, %y
%n1 = and <16 x i8> %n0, %mask
%r = xor <16 x i8> %n1, %y
ret <16 x i8> %r
}
define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {
; CHECK-LABEL: in_v8i16(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<29>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [in_v8i16_param_0];
; CHECK-NEXT: ld.param.v4.u32 {%r5, %r6, %r7, %r8}, [in_v8i16_param_1];
; CHECK-NEXT: xor.b32 %r9, %r4, %r8;
; CHECK-NEXT: xor.b32 %r10, %r3, %r7;
; CHECK-NEXT: xor.b32 %r11, %r2, %r6;
; CHECK-NEXT: xor.b32 %r12, %r1, %r5;
; CHECK-NEXT: ld.param.v4.u32 {%r13, %r14, %r15, %r16}, [in_v8i16_param_2];
; CHECK-NEXT: and.b32 %r17, %r12, %r13;
; CHECK-NEXT: and.b32 %r18, %r11, %r14;
; CHECK-NEXT: and.b32 %r19, %r10, %r15;
; CHECK-NEXT: and.b32 %r20, %r9, %r16;
; CHECK-NEXT: xor.b32 %r21, %r20, %r8;
; CHECK-NEXT: xor.b32 %r23, %r19, %r7;
; CHECK-NEXT: xor.b32 %r25, %r18, %r6;
; CHECK-NEXT: xor.b32 %r27, %r17, %r5;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r27, %r25, %r23, %r21};
; CHECK-NEXT: ret;
%n0 = xor <8 x i16> %x, %y
%n1 = and <8 x i16> %n0, %mask
%r = xor <8 x i16> %n1, %y
ret <8 x i16> %r
}
define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
; CHECK-LABEL: in_v4i32(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<25>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [in_v4i32_param_0];
; CHECK-NEXT: ld.param.v4.u32 {%r5, %r6, %r7, %r8}, [in_v4i32_param_1];
; CHECK-NEXT: xor.b32 %r9, %r4, %r8;
; CHECK-NEXT: xor.b32 %r10, %r3, %r7;
; CHECK-NEXT: xor.b32 %r11, %r2, %r6;
; CHECK-NEXT: xor.b32 %r12, %r1, %r5;
; CHECK-NEXT: ld.param.v4.u32 {%r13, %r14, %r15, %r16}, [in_v4i32_param_2];
; CHECK-NEXT: and.b32 %r17, %r12, %r13;
; CHECK-NEXT: and.b32 %r18, %r11, %r14;
; CHECK-NEXT: and.b32 %r19, %r10, %r15;
; CHECK-NEXT: and.b32 %r20, %r9, %r16;
; CHECK-NEXT: xor.b32 %r21, %r20, %r8;
; CHECK-NEXT: xor.b32 %r22, %r19, %r7;
; CHECK-NEXT: xor.b32 %r23, %r18, %r6;
; CHECK-NEXT: xor.b32 %r24, %r17, %r5;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r24, %r23, %r22, %r21};
; CHECK-NEXT: ret;
%n0 = xor <4 x i32> %x, %y
%n1 = and <4 x i32> %n0, %mask
%r = xor <4 x i32> %n1, %y
ret <4 x i32> %r
}
define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {
; CHECK-LABEL: in_v2i64(
; CHECK: {
; CHECK-NEXT: .reg .b64 %rd<13>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u64 {%rd1, %rd2}, [in_v2i64_param_0];
; CHECK-NEXT: ld.param.v2.u64 {%rd3, %rd4}, [in_v2i64_param_1];
; CHECK-NEXT: xor.b64 %rd5, %rd2, %rd4;
; CHECK-NEXT: xor.b64 %rd6, %rd1, %rd3;
; CHECK-NEXT: ld.param.v2.u64 {%rd7, %rd8}, [in_v2i64_param_2];
; CHECK-NEXT: and.b64 %rd9, %rd6, %rd7;
; CHECK-NEXT: and.b64 %rd10, %rd5, %rd8;
; CHECK-NEXT: xor.b64 %rd11, %rd10, %rd4;
; CHECK-NEXT: xor.b64 %rd12, %rd9, %rd3;
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd12, %rd11};
; CHECK-NEXT: ret;
%n0 = xor <2 x i64> %x, %y
%n1 = and <2 x i64> %n0, %mask
%r = xor <2 x i64> %n1, %y
ret <2 x i64> %r
}