| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s |
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s |
| define <4 x i32> @test_signext_vector_inreg(<4 x i16> %n) { |
| ; CHECK-P9-LABEL: test_signext_vector_inreg: |
| ; CHECK-P9: # %bb.0: # %entry |
| ; CHECK-P9-NEXT: vmrglh 2, 2, 2 |
| ; CHECK-P9-NEXT: vextsh2w 2, 2 |
| ; CHECK-P9-NEXT: blr |
| ; |
| ; CHECK-P8-LABEL: test_signext_vector_inreg: |
| ; CHECK-P8: # %bb.0: # %entry |
| ; CHECK-P8-NEXT: vmrglh 2, 2, 2 |
| ; CHECK-P8-NEXT: vspltisw 3, 8 |
| ; CHECK-P8-NEXT: vadduwm 3, 3, 3 |
| ; CHECK-P8-NEXT: vslw 2, 2, 3 |
| ; CHECK-P8-NEXT: vsraw 2, 2, 3 |
| ; CHECK-P8-NEXT: blr |
| entry: |
| %0 = sext <4 x i16> %n to <4 x i32> |
| ret <4 x i32> %0 |
| } |