test/CodeGen/AArch64/urem-seteq-illegal-types.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s

define i1 @test_urem_odd(i13 %X) nounwind {
; CHECK-LABEL: test_urem_odd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w9, #52429
; CHECK-NEXT:    and w8, w0, #0x1fff
; CHECK-NEXT:    movk w9, #52428, lsl #16
; CHECK-NEXT:    mul w8, w8, w9
; CHECK-NEXT:    mov w9, #13108
; CHECK-NEXT:    movk w9, #13107, lsl #16
; CHECK-NEXT:    cmp w8, w9
; CHECK-NEXT:    cset w0, lo
; CHECK-NEXT:    ret
  %urem = urem i13 %X, 5
  %cmp = icmp eq i13 %urem, 0
  ret i1 %cmp
}

define i1 @test_urem_even(i27 %X) nounwind {
; CHECK-LABEL: test_urem_even:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w9, #28087
; CHECK-NEXT:    and w8, w0, #0x7ffffff
; CHECK-NEXT:    movk w9, #46811, lsl #16
; CHECK-NEXT:    mul w8, w8, w9
; CHECK-NEXT:    mov w9, #9363
; CHECK-NEXT:    ror w8, w8, #1
; CHECK-NEXT:    movk w9, #4681, lsl #16
; CHECK-NEXT:    cmp w8, w9
; CHECK-NEXT:    cset w0, lo
; CHECK-NEXT:    ret
  %urem = urem i27 %X, 14
  %cmp = icmp eq i27 %urem, 0
  ret i1 %cmp
}

define i1 @test_urem_odd_setne(i4 %X) nounwind {
; CHECK-LABEL: test_urem_odd_setne:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w9, #52429
; CHECK-NEXT:    and w8, w0, #0xf
; CHECK-NEXT:    movk w9, #52428, lsl #16
; CHECK-NEXT:    mul w8, w8, w9
; CHECK-NEXT:    mov w9, #858993459
; CHECK-NEXT:    cmp w8, w9
; CHECK-NEXT:    cset w0, hi
; CHECK-NEXT:    ret
  %urem = urem i4 %X, 5
  %cmp = icmp ne i4 %urem, 0
  ret i1 %cmp
}

define i1 @test_urem_negative_odd(i9 %X) nounwind {
; CHECK-LABEL: test_urem_negative_odd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w9, #57651
; CHECK-NEXT:    and w8, w0, #0x1ff
; CHECK-NEXT:    movk w9, #43302, lsl #16
; CHECK-NEXT:    mul w8, w8, w9
; CHECK-NEXT:    mov w9, #17191
; CHECK-NEXT:    movk w9, #129, lsl #16
; CHECK-NEXT:    cmp w8, w9
; CHECK-NEXT:    cset w0, hi
; CHECK-NEXT:    ret
  %urem = urem i9 %X, -5
  %cmp = icmp ne i9 %urem, 0
  ret i1 %cmp
}

define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
; CHECK-LABEL: test_urem_vec:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w12, #43691
; CHECK-NEXT:    and w8, w0, #0x7ff
; CHECK-NEXT:    movk w12, #43690, lsl #16
; CHECK-NEXT:    umull x12, w8, w12
; CHECK-NEXT:    mov w11, #25663
; CHECK-NEXT:    mov w13, #6
; CHECK-NEXT:    lsr x12, x12, #34
; CHECK-NEXT:    and w10, w2, #0x7ff
; CHECK-NEXT:    movk w11, #160, lsl #16
; CHECK-NEXT:    msub w8, w12, w13, w8
; CHECK-NEXT:    mov w12, #18725
; CHECK-NEXT:    and w9, w1, #0x7ff
; CHECK-NEXT:    movk w12, #9362, lsl #16
; CHECK-NEXT:    umull x11, w10, w11
; CHECK-NEXT:    adrp x13, .LCPI4_0
; CHECK-NEXT:    umull x12, w9, w12
; CHECK-NEXT:    lsr x11, x11, #32
; CHECK-NEXT:    ldr d0, [x13, :lo12:.LCPI4_0]
; CHECK-NEXT:    lsr x12, x12, #32
; CHECK-NEXT:    sub w13, w10, w11
; CHECK-NEXT:    add w11, w11, w13, lsr #1
; CHECK-NEXT:    sub w13, w9, w12
; CHECK-NEXT:    add w12, w12, w13, lsr #1
; CHECK-NEXT:    fmov s1, w8
; CHECK-NEXT:    mov w8, #2043
; CHECK-NEXT:    lsr w11, w11, #10
; CHECK-NEXT:    lsr w12, w12, #2
; CHECK-NEXT:    msub w8, w11, w8, w10
; CHECK-NEXT:    sub w10, w12, w12, lsl #3
; CHECK-NEXT:    add w9, w9, w10
; CHECK-NEXT:    mov v1.h[1], w9
; CHECK-NEXT:    mov v1.h[2], w8
; CHECK-NEXT:    bic v1.4h, #248, lsl #8
; CHECK-NEXT:    cmeq v0.4h, v1.4h, v0.4h
; CHECK-NEXT:    mvn v0.8b, v0.8b
; CHECK-NEXT:    umov w0, v0.h[0]
; CHECK-NEXT:    umov w1, v0.h[1]
; CHECK-NEXT:    umov w2, v0.h[2]
; CHECK-NEXT:    ret
  %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
  %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
  ret <3 x i1> %cmp
}