| //=- AArch64Features.td - Describe AArch64 SubtargetFeatures -*- tablegen -*-=// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // |
| //===----------------------------------------------------------------------===// |
| |
| // Each SubtargetFeature which corresponds to an Arm Architecture feature should |
| // be annotated with the respective FEAT_ feature name from the Architecture |
| // Reference Manual. If a SubtargetFeature enables instructions from multiple |
| // Arm Architecture Features, it should list all the relevant features. Not all |
| // FEAT_ features have a corresponding SubtargetFeature. |
| |
| def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", |
| "Enable ARMv8 FP (FEAT_FP)">; |
| |
| def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", |
| "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; |
| |
| def FeatureSM4 : SubtargetFeature< |
| "sm4", "HasSM4", "true", |
| "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; |
| |
| def FeatureSHA2 : SubtargetFeature< |
| "sha2", "HasSHA2", "true", |
| "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; |
| |
| def FeatureSHA3 : SubtargetFeature< |
| "sha3", "HasSHA3", "true", |
| "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; |
| |
| def FeatureAES : SubtargetFeature< |
| "aes", "HasAES", "true", |
| "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; |
| |
| // Crypto has been split up and any combination is now valid (see the |
| // crypto definitions above). Also, crypto is now context sensitive: |
| // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. |
| // Therefore, we rely on Clang, the user interfacing tool, to pass on the |
| // appropriate crypto options. But here in the backend, crypto has very little |
| // meaning anymore. We kept the Crypto definition here for backward |
| // compatibility, and now imply features SHA2 and AES, which was the |
| // "traditional" meaning of Crypto. |
| def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", |
| "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; |
| |
| def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", |
| "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; |
| |
| def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", |
| "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; |
| |
| def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true", |
| "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", |
| [FeatureRAS]>; |
| |
| def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", |
| "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; |
| |
| def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", |
| "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; |
| |
| def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", |
| "Enable out of line atomics to support LSE instructions">; |
| |
| def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", |
| "Enable Function Multi Versioning support.">; |
| |
| def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", |
| "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)", |
| [FeatureNEON]>; |
| |
| def FeaturePAN : SubtargetFeature< |
| "pan", "HasPAN", "true", |
| "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; |
| |
| def FeatureLOR : SubtargetFeature< |
| "lor", "HasLOR", "true", |
| "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; |
| |
| def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", |
| "true", "Enable RW operand CONTEXTIDR_EL2" >; |
| |
| def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", |
| "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; |
| |
| // This SubtargetFeature is special. It controls only whether codegen will turn |
| // `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The |
| // `FEAT_PMUv3*` system registers are always available for assembly/disassembly. |
| def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", |
| "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; |
| |
| def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", |
| "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; |
| |
| def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", |
| "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; |
| |
| def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", |
| "Enable Statistical Profiling extension (FEAT_SPE)">; |
| |
| def FeaturePAN_RWV : SubtargetFeature< |
| "pan-rwv", "HasPAN_RWV", "true", |
| "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", |
| [FeaturePAN]>; |
| |
| // UAO PState |
| def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", |
| "Enable v8.2 UAO PState (FEAT_UAO)">; |
| |
| def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", |
| "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; |
| |
| def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", |
| "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; |
| |
| def FeatureFPMR : SubtargetFeature<"fpmr", "HasFPMR", "true", |
| "Enable FPMR Register (FEAT_FPMR)">; |
| |
| def FeatureFP8 : SubtargetFeature<"fp8", "HasFP8", "true", |
| "Enable FP8 instructions (FEAT_FP8)">; |
| |
| // This flag is currently still labeled as Experimental, but when fully |
| // implemented this should tell the compiler to use the zeroing pseudos to |
| // benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive |
| // lanes are known to be zero. The pseudos will then be expanded using the |
| // MOVPRFX instruction to zero the inactive lanes. This feature should only be |
| // enabled if MOVPRFX instructions are known to merge with the destructive |
| // operations they prefix. |
| // |
| // This feature could similarly be extended to support cheap merging of _any_ |
| // value into the inactive lanes using the MOVPRFX instruction that uses |
| // merging-predication. |
| def FeatureExperimentalZeroingPseudos |
| : SubtargetFeature<"use-experimental-zeroing-pseudos", |
| "UseExperimentalZeroingPseudos", "true", |
| "Hint to the compiler that the MOVPRFX instruction is " |
| "merged with destructive operations", |
| []>; |
| |
| def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", |
| "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; |
| |
| def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", |
| "true", "Enable BFloat16 Extension (FEAT_BF16)" >; |
| |
| def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r", |
| "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">; |
| |
| def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", |
| "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", |
| [FeatureSVE, FeatureUseScalarIncVL]>; |
| |
| def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", |
| "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", |
| [FeatureSVE2, FeatureAES]>; |
| |
| def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", |
| "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; |
| |
| def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", |
| "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; |
| |
| def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", |
| "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; |
| |
| def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true", |
| "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; |
| |
| def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true", |
| "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>; |
| |
| def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", |
| "Has zero-cycle register moves">; |
| |
| def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", |
| "Has zero-cycle zeroing instructions for generic registers">; |
| |
| // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". |
| // as movi is more efficient across all cores. Newer cores can eliminate |
| // fmovs early and there is no difference with movi, but this not true for |
| // all implementations. |
| def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", |
| "Has no zero-cycle zeroing instructions for FP registers">; |
| |
| def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", |
| "Has zero-cycle zeroing instructions", |
| [FeatureZCZeroingGP]>; |
| |
| /// ... but the floating-point version doesn't quite work in rare cases on older |
| /// CPUs. |
| def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", |
| "HasZeroCycleZeroingFPWorkaround", "true", |
| "The zero-cycle floating-point zeroing instruction has a bug">; |
| |
| def FeatureStrictAlign : SubtargetFeature<"strict-align", |
| "RequiresStrictAlign", "true", |
| "Disallow all unaligned memory " |
| "access">; |
| |
| foreach i = {1-7,9-15,18,20-28} in |
| def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", |
| "Reserve X"#i#", making it unavailable " |
| "as a GPR">; |
| |
| foreach i = {8-15,18} in |
| def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, |
| "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; |
| |
| def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", |
| "true", |
| "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; |
| |
| def FeaturePredictableSelectIsExpensive : SubtargetFeature< |
| "predictable-select-expensive", "PredictableSelectIsExpensive", "true", |
| "Prefer likely predicted branches over selects">; |
| |
| def FeatureEnableSelectOptimize : SubtargetFeature< |
| "enable-select-opt", "EnableSelectOptimize", "true", |
| "Enable the select optimize pass for select loop heuristics">; |
| |
| def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", |
| "HasExynosCheapAsMoveHandling", "true", |
| "Use Exynos specific handling of cheap instructions">; |
| |
| def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", |
| "UsePostRAScheduler", "true", "Schedule again after register allocation">; |
| |
| def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", |
| "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; |
| |
| def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", |
| "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; |
| |
| def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", |
| "IsStoreAddressAscend", "true", |
| "Schedule vector stores by ascending address">; |
| |
| def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", |
| "true", "STR of Q register with register offset is slow">; |
| |
| def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< |
| "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", |
| "true", "Use alternative pattern for sextload convert to f32">; |
| |
| def FeatureArithmeticBccFusion : SubtargetFeature< |
| "arith-bcc-fusion", "HasArithmeticBccFusion", "true", |
| "CPU fuses arithmetic+bcc operations">; |
| |
| def FeatureArithmeticCbzFusion : SubtargetFeature< |
| "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", |
| "CPU fuses arithmetic + cbz/cbnz operations">; |
| |
| def FeatureCmpBccFusion : SubtargetFeature< |
| "cmp-bcc-fusion", "HasCmpBccFusion", "true", |
| "CPU fuses cmp+bcc operations">; |
| |
| def FeatureFuseAddress : SubtargetFeature< |
| "fuse-address", "HasFuseAddress", "true", |
| "CPU fuses address generation and memory operations">; |
| |
| def FeatureFuseAES : SubtargetFeature< |
| "fuse-aes", "HasFuseAES", "true", |
| "CPU fuses AES crypto operations">; |
| |
| def FeatureFuseArithmeticLogic : SubtargetFeature< |
| "fuse-arith-logic", "HasFuseArithmeticLogic", "true", |
| "CPU fuses arithmetic and logic operations">; |
| |
| def FeatureFuseCCSelect : SubtargetFeature< |
| "fuse-csel", "HasFuseCCSelect", "true", |
| "CPU fuses conditional select operations">; |
| |
| def FeatureFuseCryptoEOR : SubtargetFeature< |
| "fuse-crypto-eor", "HasFuseCryptoEOR", "true", |
| "CPU fuses AES/PMULL and EOR operations">; |
| |
| def FeatureFuseAdrpAdd : SubtargetFeature< |
| "fuse-adrp-add", "HasFuseAdrpAdd", "true", |
| "CPU fuses adrp+add operations">; |
| |
| def FeatureFuseLiterals : SubtargetFeature< |
| "fuse-literals", "HasFuseLiterals", "true", |
| "CPU fuses literal generation operations">; |
| |
| def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature< |
| "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true", |
| "CPU fuses (a + b + 1) and (a - b - 1)">; |
| |
| def FeatureDisableLatencySchedHeuristic : SubtargetFeature< |
| "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", |
| "Disable latency scheduling heuristic">; |
| |
| def FeatureStorePairSuppress : SubtargetFeature< |
| "store-pair-suppress", "EnableStorePairSuppress", "true", |
| "Enable Store Pair Suppression heuristics">; |
| |
| def FeatureForce32BitJumpTables |
| : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", |
| "Force jump table entries to be 32-bits wide except at MinSize">; |
| |
| def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", |
| "Enable support for RCPC extension (FEAT_LRCPC)">; |
| |
| def FeatureUseRSqrt : SubtargetFeature< |
| "use-reciprocal-square-root", "UseRSqrt", "true", |
| "Use the reciprocal square root approximation">; |
| |
| def FeatureDotProd : SubtargetFeature< |
| "dotprod", "HasDotProd", "true", |
| "Enable dot product support (FEAT_DotProd)", [FeatureNEON]>; |
| |
| def FeaturePAuth : SubtargetFeature< |
| "pauth", "HasPAuth", "true", |
| "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; |
| |
| def FeatureJS : SubtargetFeature< |
| "jsconv", "HasJS", "true", |
| "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", |
| [FeatureFPARMv8]>; |
| |
| def FeatureCCIDX : SubtargetFeature< |
| "ccidx", "HasCCIDX", "true", |
| "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; |
| |
| def FeatureComplxNum : SubtargetFeature< |
| "complxnum", "HasComplxNum", "true", |
| "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", |
| [FeatureNEON]>; |
| |
| def FeatureNV : SubtargetFeature< |
| "nv", "HasNV", "true", |
| "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">; |
| |
| def FeatureMPAM : SubtargetFeature< |
| "mpam", "HasMPAM", "true", |
| "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">; |
| |
| def FeatureDIT : SubtargetFeature< |
| "dit", "HasDIT", "true", |
| "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">; |
| |
| def FeatureTRACEV8_4 : SubtargetFeature< |
| "tracev8.4", "HasTRACEV8_4", "true", |
| "Enable v8.4-A Trace extension (FEAT_TRF)">; |
| |
| def FeatureAM : SubtargetFeature< |
| "am", "HasAM", "true", |
| "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">; |
| |
| def FeatureAMVS : SubtargetFeature< |
| "amvs", "HasAMVS", "true", |
| "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", |
| [FeatureAM]>; |
| |
| def FeatureSEL2 : SubtargetFeature< |
| "sel2", "HasSEL2", "true", |
| "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">; |
| |
| def FeatureTLB_RMI : SubtargetFeature< |
| "tlb-rmi", "HasTLB_RMI", "true", |
| "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">; |
| |
| def FeatureFlagM : SubtargetFeature< |
| "flagm", "HasFlagM", "true", |
| "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; |
| |
| // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset |
| def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", |
| "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", |
| [FeatureRCPC]>; |
| |
| def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", |
| "NegativeImmediates", "false", |
| "Convert immediates and instructions " |
| "to their negated or complemented " |
| "equivalent when the immediate does " |
| "not fit in the encoding.">; |
| |
| // Address operands with shift amount 2 or 3 are fast on all Arm chips except |
| // some old Apple cores (A7-A10?) which handle all shifts slowly. Cortex-A57 |
| // and derived designs through Cortex-X1 take an extra micro-op for shifts |
| // of 1 or 4. Other Arm chips handle all shifted operands at the same speed |
| // as unshifted operands. |
| // |
| // We don't try to model the behavior of the old Apple cores because new code |
| // targeting A7 is very unlikely to actually run on an A7. The Cortex cores |
| // are modeled by FeatureAddrLSLSlow14. |
| def FeatureAddrLSLSlow14 : SubtargetFeature< |
| "addr-lsl-slow-14", "HasAddrLSLSlow14", "true", |
| "Address operands with shift amount of 1 or 4 are slow">; |
| |
| def FeatureALULSLFast : SubtargetFeature< |
| "alu-lsl-fast", "HasALULSLFast", "true", |
| "Add/Sub operations with lsl shift <= 4 are cheap">; |
| |
| def FeatureAggressiveFMA : |
| SubtargetFeature<"aggressive-fma", |
| "HasAggressiveFMA", |
| "true", |
| "Enable Aggressive FMA for floating-point.">; |
| |
| def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", |
| "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">; |
| |
| def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", |
| "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " |
| "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >; |
| |
| def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", |
| "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; |
| |
| def FeatureSB : SubtargetFeature<"sb", "HasSB", |
| "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >; |
| |
| def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", |
| "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; |
| |
| def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", |
| "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; |
| |
| def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", |
| "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; |
| |
| def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", |
| "true", "Enable Branch Target Identification (FEAT_BTI)" >; |
| |
| def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", |
| "true", "Enable Random Number generation instructions (FEAT_RNG)" >; |
| |
| def FeatureMTE : SubtargetFeature<"mte", "HasMTE", |
| "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; |
| |
| def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", |
| "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; |
| |
| def FeatureETE : SubtargetFeature<"ete", "HasETE", |
| "true", "Enable Embedded Trace Extension (FEAT_ETE)", |
| [FeatureTRBE]>; |
| |
| def FeatureTME : SubtargetFeature<"tme", "HasTME", |
| "true", "Enable Transactional Memory Extension (FEAT_TME)" >; |
| |
| def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", |
| "AllowTaggedGlobals", |
| "true", "Use an instruction sequence for taking the address of a global " |
| "that allows a memory tag in the upper address bits">; |
| |
| def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", |
| "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; |
| |
| def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", |
| "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; |
| |
| def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", |
| "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; |
| |
| def FeatureXS : SubtargetFeature<"xs", "HasXS", |
| "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; |
| |
| def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", |
| "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; |
| |
| def FeatureHCX : SubtargetFeature< |
| "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; |
| |
| def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", |
| "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; |
| |
| def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", |
| "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; |
| |
| def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", |
| "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; |
| |
| def FeatureNMI : SubtargetFeature<"nmi", "HasNMI", |
| "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; |
| |
| def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", |
| "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">; |
| |
| def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", |
| "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">; |
| |
| def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", |
| "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">; |
| |
| def FeatureEnhancedCounterVirtualization : |
| SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", |
| "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; |
| |
| def FeatureRME : SubtargetFeature<"rme", "HasRME", |
| "true", "Enable Realm Management Extension (FEAT_RME)">; |
| |
| def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", |
| "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; |
| |
| def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", |
| "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; |
| |
| def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", |
| "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; |
| |
| def FeatureSMEFA64 : SubtargetFeature<"sme-fa64", "HasSMEFA64", "true", |
| "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>; |
| |
| def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", |
| "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; |
| |
| def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", |
| "Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>; |
| |
| def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", |
| "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; |
| |
| def FeatureFAMINMAX: SubtargetFeature<"faminmax", "HasFAMINMAX", "true", |
| "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">; |
| |
| def FeatureFP8FMA : SubtargetFeature<"fp8fma", "HasFP8FMA", "true", |
| "Enable fp8 multiply-add instructions (FEAT_FP8FMA)">; |
| |
| def FeatureSSVE_FP8FMA : SubtargetFeature<"ssve-fp8fma", "HasSSVE_FP8FMA", "true", |
| "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>; |
| |
| def FeatureFP8DOT2: SubtargetFeature<"fp8dot2", "HasFP8DOT2", "true", |
| "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">; |
| |
| def FeatureSSVE_FP8DOT2 : SubtargetFeature<"ssve-fp8dot2", "HasSSVE_FP8DOT2", "true", |
| "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>; |
| |
| def FeatureFP8DOT4: SubtargetFeature<"fp8dot4", "HasFP8DOT4", "true", |
| "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">; |
| |
| def FeatureSSVE_FP8DOT4 : SubtargetFeature<"ssve-fp8dot4", "HasSSVE_FP8DOT4", "true", |
| "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>; |
| def FeatureLUT: SubtargetFeature<"lut", "HasLUT", "true", |
| "Enable Lookup Table instructions (FEAT_LUT)">; |
| |
| def FeatureSME_LUTv2 : SubtargetFeature<"sme-lutv2", "HasSME_LUTv2", "true", |
| "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">; |
| |
| def FeatureSMEF8F16 : SubtargetFeature<"sme-f8f16", "HasSMEF8F16", "true", |
| "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>; |
| |
| def FeatureSMEF8F32 : SubtargetFeature<"sme-f8f32", "HasSMEF8F32", "true", |
| "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>; |
| |
| def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", |
| "Apple A7 (the CPU formerly known as Cyclone)">; |
| |
| def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", |
| "Enable Exception Level 2 Virtual Memory System Architecture">; |
| |
| def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", |
| "Enable Exception Level 3">; |
| |
| def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true", |
| "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">; |
| |
| def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", |
| "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; |
| |
| def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", |
| "NoBTIAtReturnTwice", "true", |
| "Don't place a BTI instruction " |
| "after a return-twice">; |
| |
| def FeatureCHK : SubtargetFeature<"chk", "HasCHK", |
| "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">; |
| |
| def FeatureGCS : SubtargetFeature<"gcs", "HasGCS", |
| "true", "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>; |
| |
| def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", |
| "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">; |
| |
| def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", |
| "true", "Enable SLC target for PRFM instruction">; |
| |
| def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2", |
| "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", |
| [FeaturePredRes]>; |
| |
| def FeatureMEC : SubtargetFeature<"mec", "HasMEC", |
| "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; |
| |
| def FeatureITE : SubtargetFeature<"ite", "HasITE", |
| "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, |
| FeatureTRBE]>; |
| |
| def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", |
| "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", |
| [FeatureRCPC_IMMO]>; |
| |
| def FeatureTHE : SubtargetFeature<"the", "HasTHE", |
| "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; |
| |
| def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128", |
| "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", |
| [FeatureLSE]>; |
| |
| // FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit. |
| // Therefore group them all under a single feature flag, d128: |
| def FeatureD128 : SubtargetFeature<"d128", "HasD128", |
| "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers " |
| "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", |
| [FeatureLSE128]>; |
| |
| def FeatureDisableLdp : SubtargetFeature<"disable-ldp", "HasDisableLdp", |
| "true", "Do not emit ldp">; |
| |
| def FeatureDisableStp : SubtargetFeature<"disable-stp", "HasDisableStp", |
| "true", "Do not emit stp">; |
| |
| def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedOnly", |
| "true", "In order to emit ldp, first check if the load will be aligned to 2 * element_size">; |
| |
| def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly", |
| "true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">; |
| |
| // AArch64 2023 Architecture Extensions (v9.5-A) |
| |
| def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true", |
| "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">; |
| |
| def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR", |
| "true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">; |
| |
| def FeatureTLBIW : SubtargetFeature<"tlbiw", "HasTLBIW", "true", |
| "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">; |
| |
| |
| //===----------------------------------------------------------------------===// |
| // Architectures. |
| // |
| def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", |
| "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; |
| |
| def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", |
| "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, |
| FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; |
| |
| def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", |
| "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, |
| FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; |
| |
| def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", |
| "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, |
| FeatureJS, FeatureCCIDX, FeatureComplxNum]>; |
| |
| def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", |
| "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, |
| FeatureNV, FeatureMPAM, FeatureDIT, |
| FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, |
| FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; |
| |
| def HasV8_5aOps : SubtargetFeature< |
| "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", |
| [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, |
| FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, |
| FeatureBranchTargetId]>; |
| |
| def HasV8_6aOps : SubtargetFeature< |
| "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", |
| [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, |
| FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; |
| |
| def HasV8_7aOps : SubtargetFeature< |
| "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", |
| [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; |
| |
| def HasV8_8aOps : SubtargetFeature< |
| "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", |
| [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; |
| |
| def HasV8_9aOps : SubtargetFeature< |
| "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", |
| [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, |
| FeatureCSSC, FeatureRASv2, FeatureCHK]>; |
| |
| def HasV9_0aOps : SubtargetFeature< |
| "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", |
| [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; |
| |
| def HasV9_1aOps : SubtargetFeature< |
| "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", |
| [HasV8_6aOps, HasV9_0aOps]>; |
| |
| def HasV9_2aOps : SubtargetFeature< |
| "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", |
| [HasV8_7aOps, HasV9_1aOps]>; |
| |
| def HasV9_3aOps : SubtargetFeature< |
| "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", |
| [HasV8_8aOps, HasV9_2aOps]>; |
| |
| def HasV9_4aOps : SubtargetFeature< |
| "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", |
| [HasV8_9aOps, HasV9_3aOps]>; |
| |
| def HasV9_5aOps : SubtargetFeature< |
| "v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions", |
| [HasV9_4aOps, FeatureCPA]>; |
| |
| def HasV8_0rOps : SubtargetFeature< |
| "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", |
| [//v8.1 |
| FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2, |
| //v8.2 |
| FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, |
| //v8.3 |
| FeatureCCIDX, FeaturePAuth, FeatureRCPC, |
| //v8.4 |
| FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, |
| FeatureRCPC_IMMO, |
| // Not mandatory in v8.0-R, but included here on the grounds that it |
| // only enables names of system registers |
| FeatureSpecRestrict |
| ]>; |
| |
| //===----------------------------------------------------------------------===// |
| // Access to privileged registers |
| //===----------------------------------------------------------------------===// |
| |
| foreach i = 1-3 in |
| def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", |
| "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; |
| def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP", |
| "true", "Permit use of TPIDRRO_EL0 for the TLS base">; |
| |
| //===----------------------------------------------------------------------===// |
| // Control codegen mitigation against Straight Line Speculation vulnerability. |
| //===----------------------------------------------------------------------===// |
| |
| def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", |
| "HardenSlsRetBr", "true", |
| "Harden against straight line speculation across RET and BR instructions">; |
| def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", |
| "HardenSlsBlr", "true", |
| "Harden against straight line speculation across BLR instructions">; |
| def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", |
| "HardenSlsNoComdat", "true", |
| "Generate thunk code for SLS mitigation in the normal text section">; |
| |
| |
| // Only intended to be used by disassemblers. |
| def FeatureAll |
| : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>; |
