| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 |
| --- |
| name: ctpop_i32 |
| alignment: 4 |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0 |
| |
| ; MIPS32-LABEL: name: ctpop_i32 |
| ; MIPS32: liveins: $a0 |
| ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 |
| ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) |
| ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] |
| ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]] |
| ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) |
| ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]] |
| ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]] |
| ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] |
| ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32) |
| ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]] |
| ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]] |
| ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]] |
| ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) |
| ; MIPS32: $v0 = COPY [[LSHR3]](s32) |
| ; MIPS32: RetRA implicit $v0 |
| %0:_(s32) = COPY $a0 |
| %1:_(s32) = G_CTPOP %0(s32) |
| $v0 = COPY %1(s32) |
| RetRA implicit $v0 |
| |
| ... |
| --- |
| name: ctpop_i64 |
| alignment: 4 |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $a0, $a1 |
| |
| ; MIPS32-LABEL: name: ctpop_i64 |
| ; MIPS32: liveins: $a0, $a1 |
| ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 |
| ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 |
| ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32) |
| ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 |
| ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] |
| ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]] |
| ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 |
| ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32) |
| ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 |
| ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]] |
| ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]] |
| ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]] |
| ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 |
| ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32) |
| ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]] |
| ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 |
| ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]] |
| ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 |
| ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]] |
| ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 |
| ; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32) |
| ; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32) |
| ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]] |
| ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[AND4]] |
| ; MIPS32: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32) |
| ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]] |
| ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C3]] |
| ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] |
| ; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32) |
| ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]] |
| ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]] |
| ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]] |
| ; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32) |
| ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]] |
| ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; MIPS32: $v0 = COPY [[ADD4]](s32) |
| ; MIPS32: $v1 = COPY [[C8]](s32) |
| ; MIPS32: RetRA implicit $v0, implicit $v1 |
| %1:_(s32) = COPY $a0 |
| %2:_(s32) = COPY $a1 |
| %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) |
| %3:_(s64) = G_CTPOP %0(s64) |
| %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) |
| $v0 = COPY %4(s32) |
| $v1 = COPY %5(s32) |
| RetRA implicit $v0, implicit $v1 |
| |
| ... |