commit 84bbf824ba9385bd0642fd130d1f7f68fa3a2f03
author Benjamin Kramer <benny.kra@googlemail.com> Thu Feb 18 11:42:36 2021 +0100
committer Copybara-Service <copybara-worker@google.com> Fri Feb 19 03:27:37 2021 -0800
tree 812d2c9c519344f600b34b5bf8b9150a125544ed
parent 0d3db118ef8e6b0e6d9b9ecf143b0c81a3acf76e

[RISCV] Rewrite assert to not give unused variable warnings in Release builds

NFCI

GitOrigin-RevId: ae1e6c35570116607a4895120e6c0a524bc66b1b

lib/Target/RISCV/RISCVISelDAGToDAG.cpp

diff --git a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 1c3d0cf..fba8da6 100644
--- a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -835,10 +835,9 @@
       // If we haven't set a SubRegIdx, then we must be going between LMUL<=1
       // types (VR -> VR). This can be done as a copy.
       if (SubRegIdx == RISCV::NoSubRegister) {
-        unsigned RegClassID = getRegClassIDForVecVT(VT);
         unsigned InRegClassID = getRegClassIDForVecVT(InVT);
-        assert(RegClassID == InRegClassID &&
-               RegClassID == RISCV::VRRegClassID &&
+        assert(getRegClassIDForVecVT(VT) == RISCV::VRRegClassID &&
+               InRegClassID == RISCV::VRRegClassID &&
                "Unexpected subvector extraction");
         SDValue RC =
             CurDAG->getTargetConstant(InRegClassID, DL, Subtarget->getXLenVT());