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//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Basic SystemZ instruction definition
//===----------------------------------------------------------------------===//
class InstSystemZ<int size, dag outs, dag ins, string asmstr,
list<dag> pattern> : Instruction {
let Namespace = "SystemZ";
dag OutOperandList = outs;
dag InOperandList = ins;
let Size = size;
let Pattern = pattern;
let AsmString = asmstr;
let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
// Some instructions come in pairs, one having a 12-bit displacement
// and the other having a 20-bit displacement. Both instructions in
// the pair have the same DispKey and their DispSizes are "12" and "20"
// respectively.
string DispKey = "";
string DispSize = "none";
// Many register-based <INSN>R instructions have a memory-based <INSN>
// counterpart. OpKey uniquely identifies <INSN>R, while OpType is
// "reg" for <INSN>R and "mem" for <INSN>.
string OpKey = "";
string OpType = "none";
// MemKey identifies a targe reg-mem opcode, while MemType can be either
// "pseudo" or "target". This is used to map a pseduo memory instruction to
// its corresponding target opcode. See comment at MemFoldPseudo.
string MemKey = "";
string MemType = "none";
// Many distinct-operands instructions have older 2-operand equivalents.
// NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
// with NumOpsValue being "2" or "3" as appropriate.
string NumOpsKey = "";
string NumOpsValue = "none";
// True if this instruction is a simple D(X,B) load of a register
// (with no sign or zero extension).
bit SimpleBDXLoad = 0;
// True if this instruction is a simple D(X,B) store of a register
// (with no truncation).
bit SimpleBDXStore = 0;
// True if this instruction has a 20-bit displacement field.
bit Has20BitOffset = 0;
// True if addresses in this instruction have an index register.
bit HasIndex = 0;
// True if this is a 128-bit pseudo instruction that combines two 64-bit
// operations.
bit Is128Bit = 0;
// The access size of all memory operands in bytes, or 0 if not known.
bits<5> AccessBytes = 0;
// If the instruction sets CC to a useful value, this gives the mask
// of all possible CC results. The mask has the same form as
// SystemZ::CCMASK_*.
bits<4> CCValues = 0;
// The subset of CCValues that have the same meaning as they would after a
// comparison of the first operand against zero. "Logical" instructions
// leave this blank as they set CC in a different way.
bits<4> CompareZeroCCMask = 0;
// True if the instruction is conditional and if the CC mask operand
// comes first (as for BRC, etc.).
bit CCMaskFirst = 0;
// Similar, but true if the CC mask operand comes last (as for LOC, etc.).
bit CCMaskLast = 0;
// True if the instruction is the "logical" rather than "arithmetic" form,
// in cases where a distinction exists. Except for logical compares, if the
// instruction sets this flag along with a non-zero CCValues field, it is
// assumed to set CC to either CCMASK_LOGICAL_ZERO or
// CCMASK_LOGICAL_NONZERO.
bit IsLogical = 0;
// True if the (add or sub) instruction sets CC like a compare of the
// result against zero, but only if the 'nsw' flag is set.
bit CCIfNoSignedWrap = 0;
let TSFlags{0} = SimpleBDXLoad;
let TSFlags{1} = SimpleBDXStore;
let TSFlags{2} = Has20BitOffset;
let TSFlags{3} = HasIndex;
let TSFlags{4} = Is128Bit;
let TSFlags{9-5} = AccessBytes;
let TSFlags{13-10} = CCValues;
let TSFlags{17-14} = CompareZeroCCMask;
let TSFlags{18} = CCMaskFirst;
let TSFlags{19} = CCMaskLast;
let TSFlags{20} = IsLogical;
let TSFlags{21} = CCIfNoSignedWrap;
}
//===----------------------------------------------------------------------===//
// Mappings between instructions
//===----------------------------------------------------------------------===//
// Return the version of an instruction that has an unsigned 12-bit
// displacement.
def getDisp12Opcode : InstrMapping {
let FilterClass = "InstSystemZ";
let RowFields = ["DispKey"];
let ColFields = ["DispSize"];
let KeyCol = ["20"];
let ValueCols = [["12"]];
}
// Return the version of an instruction that has a signed 20-bit displacement.
def getDisp20Opcode : InstrMapping {
let FilterClass = "InstSystemZ";
let RowFields = ["DispKey"];
let ColFields = ["DispSize"];
let KeyCol = ["12"];
let ValueCols = [["20"]];
}
// Return the memory form of a register instruction. Note that this may
// return a MemFoldPseudo instruction (see below).
def getMemOpcode : InstrMapping {
let FilterClass = "InstSystemZ";
let RowFields = ["OpKey"];
let ColFields = ["OpType"];
let KeyCol = ["reg"];
let ValueCols = [["mem"]];
}
// Return the target memory instruction for a MemFoldPseudo.
def getTargetMemOpcode : InstrMapping {
let FilterClass = "InstSystemZ";
let RowFields = ["MemKey"];
let ColFields = ["MemType"];
let KeyCol = ["pseudo"];
let ValueCols = [["target"]];
}
// Return the 2-operand form of a 3-operand instruction.
def getTwoOperandOpcode : InstrMapping {
let FilterClass = "InstSystemZ";
let RowFields = ["NumOpsKey"];
let ColFields = ["NumOpsValue"];
let KeyCol = ["3"];
let ValueCols = [["2"]];
}
//===----------------------------------------------------------------------===//
// Instruction formats
//===----------------------------------------------------------------------===//
//
// Formats are specified using operand field declarations of the form:
//
// bits<4> Rn : register input or output for operand n
// bits<5> Vn : vector register input or output for operand n
// bits<m> In : immediate value of width m for operand n
// bits<4> BDn : address operand n, which has a base and a displacement
// bits<m> XBDn : address operand n, which has an index, a base and a
// displacement
// bits<m> VBDn : address operand n, which has a vector index, a base and a
// displacement
// bits<4> Xn : index register for address operand n
// bits<4> Mn : mode value for operand n
//
// The operand numbers ("n" in the list above) follow the architecture manual.
// Assembly operands sometimes have a different order; in particular, R3 often
// is often written between operands 1 and 2.
//
//===----------------------------------------------------------------------===//
class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
field bits<16> SoftFail = 0;
let Inst = op;
}
class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
field bits<16> SoftFail = 0;
bits<8> I1;
let Inst{15-8} = op;
let Inst{7-0} = I1;
}
class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> I1;
bits<4> I2;
let Inst{31-16} = op;
let Inst{15-8} = 0;
let Inst{7-4} = I1;
let Inst{3-0} = I2;
}
class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> M1;
bits<12> RI2;
bits<24> RI3;
let Inst{47-40} = op;
let Inst{39-36} = M1;
let Inst{35-24} = RI2;
let Inst{23-0} = RI3;
}
class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<16> I2;
let Inst{31-24} = op{11-4};
let Inst{23-20} = R1;
let Inst{19-16} = op{3-0};
let Inst{15-0} = I2;
}
class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<16> RI2;
let Inst{31-24} = op{11-4};
let Inst{23-20} = R1;
let Inst{19-16} = op{3-0};
let Inst{15-0} = RI2;
}
class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> M1;
bits<16> RI2;
let Inst{31-24} = op{11-4};
let Inst{23-20} = M1;
let Inst{19-16} = op{3-0};
let Inst{15-0} = RI2;
}
class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<16> I2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = 0;
let Inst{31-16} = I2;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> M3;
bits<16> RI4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-16} = RI4;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<8> I2;
bits<4> M3;
bits<16> RI4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-16} = RI4;
let Inst{15-8} = I2;
let Inst{7-0} = op{7-0};
}
class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<16> I2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-16} = I2;
let Inst{15-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<16> RI2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-16} = RI2;
let Inst{15-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<8> I3;
bits<8> I4;
bits<8> I5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-24} = I3;
let Inst{23-16} = I4;
let Inst{15-8} = I5;
let Inst{7-0} = op{7-0};
}
class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> M3;
bits<16> I2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-16} = I2;
let Inst{15-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<32> I2;
let Inst{47-40} = op{11-4};
let Inst{39-36} = R1;
let Inst{35-32} = op{3-0};
let Inst{31-0} = I2;
}
class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<32> RI2;
let Inst{47-40} = op{11-4};
let Inst{39-36} = R1;
let Inst{35-32} = op{3-0};
let Inst{31-0} = RI2;
}
class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> M1;
bits<32> RI2;
let Inst{47-40} = op{11-4};
let Inst{39-36} = M1;
let Inst{35-32} = op{3-0};
let Inst{31-0} = RI2;
}
class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<8> I2;
bits<4> M3;
bits<16> BD4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-16} = BD4;
let Inst{15-8} = I2;
let Inst{7-0} = op{7-0};
}
class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
field bits<16> SoftFail = 0;
bits<4> R1;
bits<4> R2;
let Inst{15-8} = op;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<4> R2;
let Inst{31-16} = op;
let Inst{15-12} = R1;
let Inst{11-8} = 0;
let Inst{7-4} = R3;
let Inst{3-0} = R2;
}
class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R2;
let Inst{31-16} = op;
let Inst{15-8} = 0;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> R3;
bits<4> M4;
let Inst{31-16} = op;
let Inst{15-12} = R3;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> R3;
bits<4> M4;
let Inst{31-16} = op;
let Inst{15-12} = R3;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> M3;
let Inst{31-16} = op;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> M4;
let Inst{31-16} = op;
let Inst{15-12} = 0;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> M3;
bits<4> M4;
let Inst{31-16} = op;
let Inst{15-12} = M3;
let Inst{11-8} = M4;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R2;
bits<4> M3;
bits<16> BD4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-16} = BD4;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<20> XBD2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
let Inst{19-0} = XBD2;
let HasIndex = 1;
}
class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> M1;
bits<20> XBD2;
let Inst{31-24} = op;
let Inst{23-20} = M1;
let Inst{19-0} = XBD2;
let HasIndex = 1;
}
class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<20> XBD2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-16} = XBD2;
let Inst{15-12} = M3;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
let HasIndex = 1;
}
class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<20> XBD2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R3;
let Inst{35-16} = XBD2;
let Inst{15-12} = R1;
let Inst{11-8} = 0;
let Inst{7-0} = op{7-0};
let HasIndex = 1;
}
class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<28> XBD2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-8} = XBD2;
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
let HasIndex = 1;
}
class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> M1;
bits<28> XBD2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = M1;
let Inst{35-8} = XBD2;
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
let HasIndex = 1;
}
class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<16> BD2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
let Inst{19-16} = R3;
let Inst{15-0} = BD2;
}
class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> M3;
bits<16> BD2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
let Inst{19-16} = M3;
let Inst{15-0} = BD2;
}
class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<16> RI2;
let Inst{31-24} = op;
let Inst{23-20} = R1;
let Inst{19-16} = R3;
let Inst{15-0} = RI2;
}
class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<20> BDL1;
let Inst{47-40} = op{15-8};
let Inst{39-36} = BDL1{19-16};
let Inst{35-32} = 0;
let Inst{31-16} = BDL1{15-0};
let Inst{15-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<24> BDL2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-16} = BDL2;
let Inst{15-12} = R1;
let Inst{11-8} = M3;
let Inst{7-0} = op{7-0};
}
class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> R3;
bits<24> BD2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-8} = BD2;
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
}
class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<4> M3;
bits<24> BD2;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = M3;
let Inst{31-8} = BD2;
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
}
class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<16> BD1;
bits<8> I2;
let Inst{31-24} = op;
let Inst{23-16} = I2;
let Inst{15-0} = BD1;
}
class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<16> BD1;
bits<16> I2;
let Inst{47-32} = op;
let Inst{31-16} = BD1;
let Inst{15-0} = I2;
}
class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<24> BD1;
bits<8> I2;
let Inst{47-40} = op{15-8};
let Inst{39-32} = I2;
let Inst{31-8} = BD1;
let Inst{7-0} = op{7-0};
let Has20BitOffset = 1;
}
class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> M1;
bits<16> RI2;
bits<16> BD3;
let Inst{47-40} = op;
let Inst{39-36} = M1;
let Inst{35-32} = 0;
let Inst{31-16} = BD3;
let Inst{15-0} = RI2;
}
class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<24> BDL1;
bits<16> BD2;
let Inst{47-40} = op;
let Inst{39-16} = BDL1;
let Inst{15-0} = BD2;
}
class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<20> BDL1;
bits<20> BDL2;
let Inst{47-40} = op;
let Inst{39-36} = BDL1{19-16};
let Inst{35-32} = BDL2{19-16};
let Inst{31-16} = BDL1{15-0};
let Inst{15-0} = BDL2{15-0};
}
class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<20> BDL1;
bits<16> BD2;
bits<4> I3;
let Inst{47-40} = op;
let Inst{39-36} = BDL1{19-16};
let Inst{35-32} = I3;
let Inst{31-16} = BDL1{15-0};
let Inst{15-0} = BD2;
}
class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<20> RBD1;
bits<16> BD2;
bits<4> R3;
let Inst{47-40} = op;
let Inst{39-36} = RBD1{19-16};
let Inst{35-32} = R3;
let Inst{31-16} = RBD1{15-0};
let Inst{15-0} = BD2;
}
class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<16> BD2;
bits<4> R3;
bits<16> BD4;
let Inst{47-40} = op;
let Inst{39-36} = R1;
let Inst{35-32} = R3;
let Inst{31-16} = BD2;
let Inst{15-0} = BD4;
}
class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<16> BD1;
bits<24> BDL2;
let Inst{47-40} = op;
let Inst{39-32} = BDL2{23-16};
let Inst{31-16} = BD1;
let Inst{15-0} = BDL2{15-0};
}
class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<16> BD1;
bits<16> BD2;
let Inst{47-32} = op;
let Inst{31-16} = BD1;
let Inst{15-0} = BD2;
}
class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<16> BD1;
bits<16> BD2;
bits<4> R3;
let Inst{47-40} = op{11-4};
let Inst{39-36} = R3;
let Inst{35-32} = op{3-0};
let Inst{31-16} = BD1;
let Inst{15-0} = BD2;
}
class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
bits<16> BD2;
let Inst{31-16} = op;
let Inst{15-0} = BD2;
}
class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<16> I2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = 0;
let Inst{31-16} = I2;
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<8> I2;
bits<8> I3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = 0;
let Inst{31-24} = I2;
let Inst{23-16} = I3;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V3;
bits<16> I2;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V3{3-0};
let Inst{31-16} = I2;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10} = V3{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<8> I4;
bits<4> M5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
let Inst{27-24} = 0;
let Inst{23-16} = I4;
let Inst{15-12} = M5;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<12> I3;
bits<4> M4;
bits<4> M5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-20} = I3;
let Inst{19-16} = M5;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<8> I4;
bits<4> M5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
let Inst{27-24} = 0;
let Inst{23-20} = M5;
let Inst{19-12} = I4;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<8> I3;
bits<8> I4;
bits<4> M5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-24} = I4;
let Inst{23-20} = M5;
let Inst{19-12} = I3;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<16> I2;
bits<4> I3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = 0;
let Inst{31-16} = I2;
let Inst{15-12} = I3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<4> R2;
bits<8> I3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R2;
let Inst{31-24} = 0;
let Inst{23-20} = M4;
let Inst{19-12} = I3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
// Depending on the instruction mnemonic, certain bits may be or-ed into
// the M4 value provided as explicit operand. These are passed as m4or.
class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> m4or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<4> M3;
bits<4> M4;
bits<4> M5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-24} = 0;
let Inst{23-20} = M5;
let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3});
let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2});
let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1});
let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
// Depending on the instruction mnemonic, certain bits may be or-ed into
// the M5 value provided as explicit operand. These are passed as m5or.
class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> m5or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<4> M4;
bits<4> M5;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
let Inst{27-24} = 0;
let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3});
let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2});
let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1});
let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0});
let Inst{19-16} = 0;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<4> M4;
bits<4> M5;
bits<4> M6;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
let Inst{27-24} = 0;
let Inst{23-20} = M6;
let Inst{19-16} = M5;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = 0;
let Inst{7-0} = op{7-0};
}
// Depending on the instruction mnemonic, certain bits may be or-ed into
// the M6 value provided as explicit operand. These are passed as m6or.
class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<4> m6or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<5> V4;
bits<4> M5;
bits<4> M6;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
let Inst{27-24} = M5;
let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3});
let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2});
let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1});
let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0});
let Inst{19-16} = 0;
let Inst{15-12} = V4{3-0};
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = V4{4};
let Inst{7-0} = op{7-0};
}
class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<5> V3;
bits<5> V4;
bits<4> M5;
bits<4> M6;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V2{3-0};
let Inst{31-28} = V3{3-0};
let Inst{27-24} = M6;
let Inst{23-20} = 0;
let Inst{19-16} = M5;
let Inst{15-12} = V4{3-0};
let Inst{11} = V1{4};
let Inst{10} = V2{4};
let Inst{9} = V3{4};
let Inst{8} = V4{4};
let Inst{7-0} = op{7-0};
}
class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<4> R2;
bits<4> R3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R2;
let Inst{31-28} = R3;
let Inst{27-12} = 0;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
let Inst{47-40} = op{15-8};
let Inst{39-36} = 0;
let Inst{35-32} = V1{3-0};
let Inst{31-12} = 0;
let Inst{11} = 0;
let Inst{10} = V1{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<5> V2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = 0;
let Inst{35-32} = V1{3-0};
let Inst{31-28} = V2{3-0};
let Inst{27-24} = 0;
let Inst{23-20} = M3;
let Inst{19-12} = 0;
let Inst{11} = 0;
let Inst{10} = V1{4};
let Inst{9} = V2{4};
let Inst{8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<5> V2;
bits<4> M3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = V2{3-0};
let Inst{31-24} = 0;
let Inst{23-20} = M3;
let Inst{19-16} = M4;
let Inst{15-12} = 0;
let Inst{11} = 0;
let Inst{10} = V2{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<16> BD2;
bits<5> V3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = V3{3-0};
let Inst{31-16} = BD2;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10} = V3{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<16> BD2;
bits<4> R3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-32} = R3;
let Inst{31-16} = BD2;
let Inst{15-12} = M4;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<4> R1;
bits<16> BD2;
bits<5> V3;
bits<4> M4;
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = V3{3-0};
let Inst{31-16} = BD2;
let Inst{15-12} = M4;
let Inst{11} = 0;
let Inst{10} = V3{4};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<16> BD2;
bits<4> R3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = 0;
let Inst{35-32} = R3;
let Inst{31-16} = BD2;
let Inst{15-12} = V1{3-0};
let Inst{11-9} = 0;
let Inst{8} = V1{4};
let Inst{7-0} = op{7-0};
}
class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<21> VBD2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-16} = VBD2{19-0};
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10} = VBD2{20};
let Inst{9-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<20> XBD2;
bits<4> M3;
let Inst{47-40} = op{15-8};
let Inst{39-36} = V1{3-0};
let Inst{35-16} = XBD2;
let Inst{15-12} = M3;
let Inst{11} = V1{4};
let Inst{10-8} = 0;
let Inst{7-0} = op{7-0};
}
class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
bits<5> V1;
bits<16> BD2;
bits<8> I3;
let Inst{47-40} = op{15-8};
let Inst{39-32} = I3;
let Inst{31-16} = BD2;
let Inst{15-12} = V1{3-0};
let Inst{11-9} = 0;
let Inst{8} = V1{4};
let Inst{7-0} = op{7-0};
}
//===----------------------------------------------------------------------===//
// Instruction classes for .insn directives
//===----------------------------------------------------------------------===//
class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstE<0, outs, ins, asmstr, pattern> {
bits<16> enc;
let Inst = enc;
}
class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRIa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
let Inst{19-16} = enc{19-16};
}
class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRIEd<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRILa<0, outs, ins, asmstr, pattern> {
bits<48> enc;
string type;
let Inst{47-40} = enc{47-40};
let Inst{35-32} = enc{35-32};
}
class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRIS<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRR<0, outs, ins, asmstr, pattern> {
bits<16> enc;
let Inst{15-8} = enc{15-8};
}
class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRRE<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-16} = enc{31-16};
}
class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRRFa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-16} = enc{31-16};
}
class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRRS<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRSa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
}
// RSE is like RSY except with a 12 bit displacement (instead of 20).
class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRSYa<6, outs, ins, asmstr, pattern> {
bits <48> enc;
let Inst{47-40} = enc{47-40};
let Inst{31-16} = BD2{15-0};
let Inst{15-8} = 0;
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRSI<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
}
class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRSYa<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRXa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
}
class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRXE<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let M3 = 0;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRXF<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstRXYa<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstS<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-16} = enc{31-16};
}
class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSI<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-24} = enc{31-24};
}
class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSIY<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSIL<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-32} = enc{47-32};
}
class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSSd<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
}
class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSSE<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-32} = enc{47-32};
}
class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSSF<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{35-32} = enc{35-32};
}
class DirectiveInsnVRI<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVRIe<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnVRR<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVRRc<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnVRS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVRSc<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVRV<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnVRX<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVRX<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstVSI<0, outs, ins, asmstr, pattern> {
bits<48> enc;
let Inst{47-40} = enc{47-40};
let Inst{7-0} = enc{7-0};
}
//===----------------------------------------------------------------------===//
// Variants of instructions with condition mask
//===----------------------------------------------------------------------===//
//
// For instructions using a condition mask (e.g. conditional branches,
// compare-and-branch instructions, or conditional move instructions),
// we generally need to create multiple instruction patterns:
//
// - One used for code generation, which encodes the condition mask as an
// MI operand, but writes out an extended mnemonic for better readability.
// - One pattern for the base form of the instruction with an explicit
// condition mask (encoded as a plain integer MI operand).
// - Specific patterns for each extended mnemonic, where the condition mask
// is implied by the pattern name and not otherwise encoded at all.
//
// We need the latter primarily for the assembler and disassembler, since the
// assembler parser is not able to decode part of an instruction mnemonic
// into an operand. Thus we provide separate patterns for each mnemonic.
//
// Note that in some cases there are two different mnemonics for the same
// condition mask. In this case we cannot have both instructions available
// to the disassembler at the same time since the encodings are not distinct.
// Therefore the alternate forms are marked isAsmParserOnly.
//
// We don't make one of the two names an alias of the other because
// we need the custom parsing routines to select the correct register class.
//
// This section provides helpers for generating the specific forms.
//
//===----------------------------------------------------------------------===//
// A class to describe a variant of an instruction with condition mask.
class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein,
string asmvariantin = ""> {
// The fixed condition mask to use.
bits<4> ccmask = ccmaskin;
// The suffix to use for the extended assembler mnemonic.
string suffix = suffixin;
// Whether this is an alternate that needs to be marked isAsmParserOnly.
bit alternate = alternatein;
// Whether this needs be to restricted to a specific dialect.
// Valid values are "att" and "hlasm", which when passed in
// will set AsmVariantName.
string asmvariant = asmvariantin;
}
// Condition mask 15 means "always true", which is used to define
// unconditional branches as a variant of conditional branches.
def CondAlways : CondVariant<15, "", 0>;
// Condition masks for general instructions that can set all 4 bits.
def CondVariantO : CondVariant<1, "o", 0>;
def CondVariantH : CondVariant<2, "h", 0>;
def CondVariantP : CondVariant<2, "p", 1>;
def CondVariantNLE : CondVariant<3, "nle", 0, "att">;
def CondVariantL : CondVariant<4, "l", 0>;
def CondVariantM : CondVariant<4, "m", 1>;
def CondVariantNHE : CondVariant<5, "nhe", 0, "att">;
def CondVariantLH : CondVariant<6, "lh", 0, "att">;
def CondVariantNE : CondVariant<7, "ne", 0>;
def CondVariantNZ : CondVariant<7, "nz", 1>;
def CondVariantE : CondVariant<8, "e", 0>;
def CondVariantZ : CondVariant<8, "z", 1>;
def CondVariantNLH : CondVariant<9, "nlh", 0, "att">;
def CondVariantHE : CondVariant<10, "he", 0, "att">;
def CondVariantNL : CondVariant<11, "nl", 0>;
def CondVariantNM : CondVariant<11, "nm", 1>;
def CondVariantLE : CondVariant<12, "le", 0, "att">;
def CondVariantNH : CondVariant<13, "nh", 0>;
def CondVariantNP : CondVariant<13, "np", 1>;
def CondVariantNO : CondVariant<14, "no", 0>;
// A helper class to look up one of the above by name.
class CV<string name>
: CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
!cast<CondVariant>("CondVariant"#name).suffix,
!cast<CondVariant>("CondVariant"#name).alternate,
!cast<CondVariant>("CondVariant"#name).asmvariant>;
// Condition masks for integer instructions (e.g. compare-and-branch).
// This is like the list above, except that condition 3 is not possible
// and that the low bit of the mask is therefore always 0. This means
// that each condition has two names. Conditions "o" and "no" are not used.
def IntCondVariantH : CondVariant<2, "h", 0>;
def IntCondVariantNLE : CondVariant<2, "nle", 1, "att">;
def IntCondVariantL : CondVariant<4, "l", 0>;
def IntCondVariantNHE : CondVariant<4, "nhe", 1, "att">;
def IntCondVariantLH : CondVariant<6, "lh", 0, "att">;
def IntCondVariantNE : CondVariant<6, "ne", 1>;
def IntCondVariantE : CondVariant<8, "e", 0>;
def IntCondVariantNLH : CondVariant<8, "nlh", 1, "att">;
def IntCondVariantHE : CondVariant<10, "he", 0, "att">;
def IntCondVariantNL : CondVariant<10, "nl", 1>;
def IntCondVariantLE : CondVariant<12, "le", 0, "att">;
def IntCondVariantNH : CondVariant<12, "nh", 1>;
// A helper class to look up one of the above by name.
class ICV<string name>
: CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
!cast<CondVariant>("IntCondVariant"#name).suffix,
!cast<CondVariant>("IntCondVariant"#name).alternate,
!cast<CondVariant>("IntCondVariant"#name).asmvariant>;
// Defines a class that makes it easier to define
// a MnemonicAlias when CondVariant's are involved.
multiclass MnemonicCondBranchAlias<CondVariant V, string from, string to,
string asmvariant = V.asmvariant> {
if !or(!eq(V.asmvariant, ""), !eq(V.asmvariant, asmvariant)) then
def "" : MnemonicAlias<!subst("#", V.suffix, from),
!subst("#", V.suffix, to),
asmvariant>;
}
//===----------------------------------------------------------------------===//
// Instruction definitions with semantics
//===----------------------------------------------------------------------===//
//
// These classes have the form [Cond]<Category><Format>, where <Format> is one
// of the formats defined above and where <Category> describes the inputs
// and outputs. "Cond" is used if the instruction is conditional,
// in which case the 4-bit condition-code mask is added as a final operand.
// <Category> can be one of:
//
// Inherent:
// One register output operand and no input operands.
//
// InherentDual:
// Two register output operands and no input operands.
//
// StoreInherent:
// One address operand. The instruction stores to the address.
//
// SideEffectInherent:
// No input or output operands, but causes some side effect.
//
// Branch:
// One branch target. The instruction branches to the target.
//
// Call:
// One output operand and one branch target. The instruction stores
// the return address to the output operand and branches to the target.
//
// CmpBranch:
// Two input operands and one optional branch target. The instruction
// compares the two input operands and branches or traps on the result.
//
// BranchUnary:
// One register output operand, one register input operand and one branch
// target. The instructions stores a modified form of the source register
// in the destination register and branches on the result.
//
// BranchBinary:
// One register output operand, two register input operands and one branch
// target. The instructions stores a modified form of one of the source
// registers in the destination register and branches on the result.
//
// LoadMultiple:
// One address input operand and two explicit output operands.
// The instruction loads a range of registers from the address,
// with the explicit operands giving the first and last register
// to load. Other loaded registers are added as implicit definitions.
//
// StoreMultiple:
// Two explicit input register operands and an address operand.
// The instruction stores a range of registers to the address,
// with the explicit operands giving the first and last register
// to store. Other stored registers are added as implicit uses.
//
// StoreLength:
// One value operand, one length operand and one address operand.
// The instruction stores the value operand to the address but
// doesn't write more than the number of bytes specified by the
// length operand.
//
// LoadAddress:
// One register output operand and one address operand.
//
// SideEffectAddress:
// One address operand. No output operands, but causes some side effect.
//
// Unary:
// One register output operand and one input operand.
//
// Store:
// One address operand and one other input operand. The instruction
// stores to the address.
//
// SideEffectUnary:
// One input operand. No output operands, but causes some side effect.
//
// Binary:
// One register output operand and two input operands.
//
// StoreBinary:
// One address operand and two other input operands. The instruction
// stores to the address.
//
// SideEffectBinary:
// Two input operands. No output operands, but causes some side effect.
//
// Compare:
// Two input operands and an implicit CC output operand.
//
// Test:
// One or two input operands and an implicit CC output operand. If
// present, the second input operand is an "address" operand used as
// a test class mask.
//
// Ternary:
// One register output operand and three input operands.
//
// SideEffectTernary:
// Three input operands. No output operands, but causes some side effect.
//
// Quaternary:
// One register output operand and four input operands.
//
// LoadAndOp:
// One output operand and two input operands, one of which is an address.
// The instruction both reads from and writes to the address.
//
// CmpSwap:
// One output operand and three input operands, one of which is an address.
// The instruction both reads from and writes to the address.
//
// RotateSelect:
// One output operand and five input operands. The first two operands
// are registers and the other three are immediates.
//
// Prefetch:
// One 4-bit immediate operand and one address operand. The immediate
// operand is 1 for a load prefetch and 2 for a store prefetch.
//
// BranchPreload:
// One 4-bit immediate operand and two address operands.
//
// The format determines which input operands are tied to output operands,
// and also determines the shape of any address operand.
//
// Multiclasses of the form <Category><Format>Pair define two instructions,
// one with <Category><Format> and one with <Category><Format>Y. The name
// of the first instruction has no suffix, the name of the second has
// an extra "y".
//
//===----------------------------------------------------------------------===//
class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
SDPatternOperator operator>
: InstRRE<opcode, (outs cls:$R1), (ins),
mnemonic#"\t$R1",
[(set cls:$R1, (operator))]> {
let R2 = 0;
}
class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
mnemonic#"\t$R1, $R2", []>;
class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
: InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
let I2 = value;
let M3 = 0;
}
class StoreInherentS<string mnemonic, bits<16> opcode,
SDPatternOperator operator, bits<5> bytes>
: InstS<opcode, (outs), (ins bdaddr12only:$BD2),
mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
let mayStore = 1;
let AccessBytes = bytes;
}
class SideEffectInherentE<string mnemonic, bits<16>opcode>
: InstE<opcode, (outs), (ins), mnemonic, []>;
class SideEffectInherentS<string mnemonic, bits<16> opcode,
SDPatternOperator operator>
: InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
let BD2 = 0;
}
class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
: InstRRE<opcode, (outs), (ins), mnemonic, []> {
let R1 = 0;
let R2 = 0;
}
// Allow an optional TLS marker symbol to generate TLS call relocations.
class CallRI<string mnemonic, bits<12> opcode>
: InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
mnemonic#"\t$R1, $RI2", []>;
// Allow an optional TLS marker symbol to generate TLS call relocations.
class CallRIL<string mnemonic, bits<12> opcode>
: InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
mnemonic#"\t$R1, $RI2", []>;
class CallRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
mnemonic#"\t$R1, $R2", []>;
class CallRX<string mnemonic, bits<8> opcode>
: InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
mnemonic#"\t$R1, $XBD2", []>;
class CondBranchRI<string mnemonic, bits<12> opcode,
SDPatternOperator operator = null_frag>
: InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
!subst("#", "${M1}", mnemonic)#"\t$RI2",
[(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
let CCMaskFirst = 1;
}
class AsmCondBranchRI<string mnemonic, bits<12> opcode>
: InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
mnemonic#"\t$M1, $RI2", []>;
class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
SDPatternOperator operator = null_frag>
: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
!subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let M1 = V.ccmask;
}
class CondBranchRIL<string mnemonic, bits<12> opcode>
: InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
!subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
let CCMaskFirst = 1;
}
class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
: InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
mnemonic#"\t$M1, $RI2", []>;
class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
!subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let M1 = V.ccmask;
}
class CondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
!subst("#", "${R1}", mnemonic)#"\t$R2", []> {
let CCMaskFirst = 1;
}
class AsmCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
mnemonic#"\t$R1, $R2", []>;
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
SDPatternOperator operator = null_frag>
: InstRR<opcode, (outs), (ins ADDR64:$R2),
!subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let R1 = V.ccmask;
}
class CondBranchRX<string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
let CCMaskFirst = 1;
}
class AsmCondBranchRX<string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let M1 = V.ccmask;
}
class CondBranchRXY<string mnemonic, bits<16> opcode>
: InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
let CCMaskFirst = 1;
let mayLoad = 1;
}
class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
: InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
mnemonic#"\t$M1, $XBD2", []> {
let mayLoad = 1;
}
class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
SDPatternOperator operator = null_frag>
: InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2",
[(operator (load bdxaddr20only:$XBD2))]> {
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let M1 = V.ccmask;
let mayLoad = 1;
}
class CmpBranchRIEa<string mnemonic, bits<16> opcode,
RegisterOperand cls, ImmOpWithPattern imm>
: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
mnemonic#"$M3\t$R1, $I2", []>;
class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
RegisterOperand cls, ImmOpWithPattern imm>
: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
mnemonic#"\t$R1, $I2, $M3", []>;
class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
RegisterOperand cls, ImmOpWithPattern imm>
: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
mnemonic#V.suffix#"\t$R1, $I2", []> {