| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK |
| ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK |
| |
| define <8 x i64> @vwsub_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) { |
| ; CHECK-LABEL: vwsub_wv_mask_v8i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a0, 42 |
| ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma |
| ; CHECK-NEXT: vmslt.vx v0, v8, a0 |
| ; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu |
| ; CHECK-NEXT: vwsub.wv v12, v12, v8, v0.t |
| ; CHECK-NEXT: vmv4r.v v8, v12 |
| ; CHECK-NEXT: ret |
| %mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42> |
| %a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer |
| %sa = sext <8 x i32> %a to <8 x i64> |
| %ret = sub <8 x i64> %y, %sa |
| ret <8 x i64> %ret |
| } |
| |
| define <8 x i64> @vwsubu_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) { |
| ; CHECK-LABEL: vwsubu_wv_mask_v8i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a0, 42 |
| ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma |
| ; CHECK-NEXT: vmslt.vx v0, v8, a0 |
| ; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu |
| ; CHECK-NEXT: vwsubu.wv v12, v12, v8, v0.t |
| ; CHECK-NEXT: vmv4r.v v8, v12 |
| ; CHECK-NEXT: ret |
| %mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42> |
| %a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer |
| %sa = zext <8 x i32> %a to <8 x i64> |
| %ret = sub <8 x i64> %y, %sa |
| ret <8 x i64> %ret |
| } |
| |
| define <8 x i64> @vwsubu_vv_mask_v8i32(<8 x i32> %x, <8 x i32> %y) { |
| ; CHECK-LABEL: vwsubu_vv_mask_v8i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a0, 42 |
| ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma |
| ; CHECK-NEXT: vmslt.vx v0, v8, a0 |
| ; CHECK-NEXT: vmv.v.i v12, 0 |
| ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 |
| ; CHECK-NEXT: vwsubu.vv v12, v10, v8 |
| ; CHECK-NEXT: vmv4r.v v8, v12 |
| ; CHECK-NEXT: ret |
| %mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42> |
| %a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer |
| %sa = zext <8 x i32> %a to <8 x i64> |
| %sy = zext <8 x i32> %y to <8 x i64> |
| %ret = sub <8 x i64> %sy, %sa |
| ret <8 x i64> %ret |
| } |
| |
| define <8 x i64> @vwsub_wv_mask_v8i32_nonzero(<8 x i32> %x, <8 x i64> %y) { |
| ; CHECK-LABEL: vwsub_wv_mask_v8i32_nonzero: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a0, 42 |
| ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma |
| ; CHECK-NEXT: vmslt.vx v0, v8, a0 |
| ; CHECK-NEXT: vmv.v.i v10, 1 |
| ; CHECK-NEXT: vmerge.vvm v16, v10, v8, v0 |
| ; CHECK-NEXT: vwsub.wv v8, v12, v16 |
| ; CHECK-NEXT: ret |
| %mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42> |
| %a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> |
| %sa = sext <8 x i32> %a to <8 x i64> |
| %ret = sub <8 x i64> %y, %sa |
| ret <8 x i64> %ret |
| } |