| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s |
| |
| --- |
| name: ds_append_s |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| ; CHECK-LABEL: name: ds_append_s |
| ; CHECK: liveins: $sgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.append), [[COPY]](p3), 0 |
| %0:_(p3) = COPY $sgpr0 |
| %1:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.append), %0, 0 |
| |
| ... |
| |
| --- |
| name: ds_append_v |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: ds_append_v |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(p3) = COPY $vgpr0 |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(p3) = V_READFIRSTLANE_B32 [[COPY]](p3), implicit $exec |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.append), [[V_READFIRSTLANE_B32_]](p3), 0 |
| %0:_(p3) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.append), %0, 0 |
| |
| ... |