commit 6b03ec73557b98bb87bfea9be97a50b9d55a4ac7
author Hsiangkai Wang <kai.wang@sifive.com> Thu Feb 18 09:33:25 2021 +0800
committer Copybara-Service <copybara-worker@google.com> Fri Feb 19 03:30:06 2021 -0800
tree 9c93b1eed67902b6ccd5b560da9631731d4f9bd2
parent a00ef2a2a38b091adb3fb1b2eb05c093513a4199

[NFC][RISCV] Use concise way to describe load/store instructions.

Differential Revision: https://reviews.llvm.org/D96923

GitOrigin-RevId: b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2

lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

diff --git a/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 2c845af..a98bb0f 100644
--- a/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -71,15 +71,9 @@
                                         VReg reg_class>
 {
   defvar load_instr =
-    !cond(!eq(vlmul.value, V_M1.value): !cast<Instruction>("VL1RE"#sew#"_V"),
-          !eq(vlmul.value, V_M2.value): !cast<Instruction>("VL2RE"#sew#"_V"),
-          !eq(vlmul.value, V_M4.value): !cast<Instruction>("VL4RE"#sew#"_V"),
-          !eq(vlmul.value, V_M8.value): !cast<Instruction>("VL8RE"#sew#"_V"));
+    !cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
   defvar store_instr =
-    !cond(!eq(vlmul.value, V_M1.value): VS1R_V,
-          !eq(vlmul.value, V_M2.value): VS2R_V,
-          !eq(vlmul.value, V_M4.value): VS4R_V,
-          !eq(vlmul.value, V_M8.value): VS8R_V);
+    !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
 
   // Load
   def : Pat<(type (load BaseAddr:$rs1)),