| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s |
| |
| declare <256 x float> @llvm.vp.fmul.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32) |
| |
| define fastcc <256 x float> @test_vp_fmul_v256f32_vv(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) { |
| ; CHECK-LABEL: test_vp_fmul_v256f32_vv: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvfmul.up %v0, %v0, %v1, %vm1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %r0 = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) |
| ret <256 x float> %r0 |
| } |
| |
| define fastcc <256 x float> @test_vp_fmul_v256f32_rv(float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) { |
| ; CHECK-LABEL: test_vp_fmul_v256f32_rv: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s1, %s1, (32)0 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvfmul.up %v0, %s0, %v0, %vm1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %xins = insertelement <256 x float> undef, float %s0, i32 0 |
| %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer |
| %r0 = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) |
| ret <256 x float> %r0 |
| } |
| |
| define fastcc <256 x float> @test_vp_fmul_v256f32_vr(<256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) { |
| ; CHECK-LABEL: test_vp_fmul_v256f32_vr: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s1, %s1, (32)0 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvfmul.up %v0, %s0, %v0, %vm1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %yins = insertelement <256 x float> undef, float %s1, i32 0 |
| %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer |
| %r0 = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) |
| ret <256 x float> %r0 |
| } |
| |
| |
| declare <256 x double> @llvm.vp.fmul.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32) |
| |
| define fastcc <256 x double> @test_vp_fmul_v256f64_vv(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) { |
| ; CHECK-LABEL: test_vp_fmul_v256f64_vv: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vfmul.d %v0, %v0, %v1, %vm1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %r0 = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) |
| ret <256 x double> %r0 |
| } |
| |
| define fastcc <256 x double> @test_vp_fmul_v256f64_rv(double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) { |
| ; CHECK-LABEL: test_vp_fmul_v256f64_rv: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s1, %s1, (32)0 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vfmul.d %v0, %s0, %v0, %vm1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %xins = insertelement <256 x double> undef, double %s0, i32 0 |
| %i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer |
| %r0 = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) |
| ret <256 x double> %r0 |
| } |
| |
| define fastcc <256 x double> @test_vp_fmul_v256f64_vr(<256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) { |
| ; CHECK-LABEL: test_vp_fmul_v256f64_vr: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s1, %s1, (32)0 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vfmul.d %v0, %s0, %v0, %vm1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %yins = insertelement <256 x double> undef, double %s1, i32 0 |
| %i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer |
| %r0 = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) |
| ret <256 x double> %r0 |
| } |