test/CodeGen/RISCV/machine-outliner-position.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV32I-MO %s
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV64I-MO %s

# Position instructions are illegal to outline. The first instruction won't be outlined
# because position instructions break the sequence.

--- |
  define void @func1(i32 %a, i32 %b) { ret void }

  define void @func2(i32 %a, i32 %b) { ret void }

  define void @func3(i32 %a, i32 %b) { ret void }
...
---
name:            func1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10, $x11
    ; RV32I-MO-LABEL: name: func1
    ; RV32I-MO: liveins: $x10, $x11
    ; RV32I-MO-NEXT: {{  $}}
    ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
    ; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
    ; RV32I-MO-NEXT: PseudoRET
    ; RV64I-MO-LABEL: name: func1
    ; RV64I-MO: liveins: $x10, $x11
    ; RV64I-MO-NEXT: {{  $}}
    ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
    ; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
    ; RV64I-MO-NEXT: PseudoRET
    $x10 = ORI $x10, 1023
    EH_LABEL <mcsymbol .Ltmp0>
    $x11 = ORI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x10 = SUB $x10, $x11
    PseudoRET
...
---
name:            func2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10, $x11
    ; RV32I-MO-LABEL: name: func2
    ; RV32I-MO: liveins: $x10, $x11
    ; RV32I-MO-NEXT: {{  $}}
    ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
    ; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
    ; RV32I-MO-NEXT: PseudoRET
    ; RV64I-MO-LABEL: name: func2
    ; RV64I-MO: liveins: $x10, $x11
    ; RV64I-MO-NEXT: {{  $}}
    ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
    ; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
    ; RV64I-MO-NEXT: PseudoRET
    $x10 = ORI $x10, 1023
    GC_LABEL <mcsymbol .Ltmp1>
    $x11 = ORI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x10 = SUB $x10, $x11
    PseudoRET
...
---
name:            func3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10, $x11
    ; RV32I-MO-LABEL: name: func3
    ; RV32I-MO: liveins: $x10, $x11
    ; RV32I-MO-NEXT: {{  $}}
    ; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
    ; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
    ; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
    ; RV32I-MO-NEXT: PseudoRET
    ; RV64I-MO-LABEL: name: func3
    ; RV64I-MO: liveins: $x10, $x11
    ; RV64I-MO-NEXT: {{  $}}
    ; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
    ; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
    ; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
    ; RV64I-MO-NEXT: PseudoRET
    $x10 = ORI $x10, 1023
    ANNOTATION_LABEL <mcsymbol .Ltmp2>
    $x11 = ORI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x10 = SUB $x10, $x11
    PseudoRET