| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s |
| |
| define amdgpu_kernel void @zext_i16_to_i32_uniform(i32 addrspace(1)* %out, i16 %a, i32 %b) { |
| ; GCN-LABEL: zext_i16_to_i32_uniform: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 |
| ; GCN-NEXT: s_mov_b32 s7, 0xf000 |
| ; GCN-NEXT: s_mov_b32 s6, -1 |
| ; GCN-NEXT: s_waitcnt lgkmcnt(0) |
| ; GCN-NEXT: s_mov_b32 s4, s0 |
| ; GCN-NEXT: s_and_b32 s0, s2, 0xffff |
| ; GCN-NEXT: s_add_i32 s0, s3, s0 |
| ; GCN-NEXT: s_mov_b32 s5, s1 |
| ; GCN-NEXT: v_mov_b32_e32 v0, s0 |
| ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; GCN-NEXT: s_endpgm |
| %zext = zext i16 %a to i32 |
| %res = add i32 %b, %zext |
| store i32 %res, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| |
| define amdgpu_kernel void @zext_i16_to_i64_uniform(i64 addrspace(1)* %out, i16 %a, i64 %b) { |
| ; GCN-LABEL: zext_i16_to_i64_uniform: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_load_dword s6, s[0:1], 0xb |
| ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd |
| ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 |
| ; GCN-NEXT: s_mov_b32 s3, 0xf000 |
| ; GCN-NEXT: s_mov_b32 s2, -1 |
| ; GCN-NEXT: s_waitcnt lgkmcnt(0) |
| ; GCN-NEXT: s_and_b32 s6, s6, 0xffff |
| ; GCN-NEXT: s_add_u32 s4, s4, s6 |
| ; GCN-NEXT: s_addc_u32 s5, s5, 0 |
| ; GCN-NEXT: v_mov_b32_e32 v0, s4 |
| ; GCN-NEXT: v_mov_b32_e32 v1, s5 |
| ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; GCN-NEXT: s_endpgm |
| %zext = zext i16 %a to i64 |
| %res = add i64 %b, %zext |
| store i64 %res, i64 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @zext_i16_to_i32_divergent(i32 addrspace(1)* %out, i16 %a, i32 %b) { |
| ; GCN-LABEL: zext_i16_to_i32_divergent: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_load_dword s4, s[0:1], 0xb |
| ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 |
| ; GCN-NEXT: s_mov_b32 s3, 0xf000 |
| ; GCN-NEXT: s_mov_b32 s2, -1 |
| ; GCN-NEXT: s_waitcnt lgkmcnt(0) |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; GCN-NEXT: s_endpgm |
| %tid = call i32 @llvm.amdgcn.workitem.id.x() |
| %tid.truncated = trunc i32 %tid to i16 |
| %divergent.a = add i16 %a, %tid.truncated |
| %zext = zext i16 %divergent.a to i32 |
| store i32 %zext, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| |
| define amdgpu_kernel void @zext_i16_to_i64_divergent(i64 addrspace(1)* %out, i16 %a, i64 %b) { |
| ; GCN-LABEL: zext_i16_to_i64_divergent: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_load_dword s4, s[0:1], 0xb |
| ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 |
| ; GCN-NEXT: s_mov_b32 s3, 0xf000 |
| ; GCN-NEXT: s_mov_b32 s2, -1 |
| ; GCN-NEXT: v_mov_b32_e32 v1, 0 |
| ; GCN-NEXT: s_waitcnt lgkmcnt(0) |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; GCN-NEXT: s_endpgm |
| %tid = call i32 @llvm.amdgcn.workitem.id.x() |
| %tid.truncated = trunc i32 %tid to i16 |
| %divergent.a = add i16 %a, %tid.truncated |
| %zext = zext i16 %divergent.a to i64 |
| store i64 %zext, i64 addrspace(1)* %out |
| ret void |
| } |
| |
| declare i32 @llvm.amdgcn.workitem.id.x() #1 |
| |
| attributes #0 = { nounwind } |
| attributes #1 = { nounwind readnone speculatable } |