| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-regalloc -start-before=machine-scheduler -stop-after=greedy,0 -o - %s | FileCheck %s |
| |
| # Make sure liveness is correctly updated when folding the cndmask and |
| # compare. |
| |
| --- |
| name: cndmask_same_block |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_same_block |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| S_BRANCH %bb.4 |
| |
| bb.2: |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %2, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_BRANCH %bb.4 |
| |
| bb.4: |
| ... |
| |
| --- |
| name: cndmask_separate_block |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_separate_block |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| S_BRANCH %bb.4 |
| |
| bb.2: |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %2, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_BRANCH %bb.4 |
| |
| bb.4: |
| ... |
| |
| --- |
| name: cndmask_same_block_other_cmpreg_use |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_same_block_other_cmpreg_use |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec |
| ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_CMP_NE_U32_e64_]] |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| S_BRANCH %bb.4 |
| |
| bb.2: |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| S_NOP 0, implicit %2 |
| $vcc = S_AND_B64 $exec, %2, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_BRANCH %bb.4 |
| |
| bb.4: |
| ... |
| |
| --- |
| name: cndmask_same_block_liveout_use |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_same_block_liveout_use |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_NOP 0, implicit [[V_CNDMASK_B32_e64_]] |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| S_BRANCH %bb.4 |
| |
| bb.2: |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %2, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_NOP 0, implicit %1 |
| S_BRANCH %bb.4 |
| |
| bb.4: |
| ... |
| |
| # The legality check for removing the compare used to rely on |
| # use_nodbg_empty, which fails on the undef use of %2. We would then |
| # fail to update the interval correctly. |
| |
| --- |
| name: cmp_reg_extra_undef_use |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cmp_reg_extra_undef_use |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def dead $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_AND_B64 $exec, undef %2:sreg_64_xexec, implicit-def dead $scc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| bb.0: |
| %0:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %0, implicit $exec |
| $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc |
| S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc |
| |
| bb.1: |
| $vcc = S_AND_B64 $exec, undef %2, implicit-def dead $scc |
| |
| bb.3: |
| |
| ... |
| |
| # use_nodbg_empty is insufficient for erasing %1's def when removing |
| # V_CNDMASK_B32. |
| |
| --- |
| name: cndmask_undef_extra_use |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_undef_extra_use |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: dead %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_NOP 0, implicit undef %1 |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| S_BRANCH %bb.4 |
| |
| bb.2: |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %2, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_NOP 0, implicit undef %1 |
| S_BRANCH %bb.4 |
| |
| bb.4: |
| ... |
| |
| --- |
| name: cndmask_is_undef |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_is_undef |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: dead %0:sreg_64_xexec = S_MOV_B64 0 |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, undef %0, implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.4(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.4 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = S_MOV_B64 0 |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc |
| S_BRANCH %bb.4 |
| |
| bb.2: |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %2, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_BRANCH %bb.4 |
| |
| bb.4: |
| ... |
| |
| # Liveness of V_CNDMASK_B32 source (%0) must be extended through loop. |
| |
| --- |
| name: cndmask_loop_cndmask |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_loop_cndmask |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], -1, implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.4, implicit $scc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF1]], implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| bb.0: |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| %1:sreg_32 = IMPLICIT_DEF |
| %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc |
| |
| bb.1: |
| %1:sreg_32 = S_ADD_I32 %1, -1, implicit-def $scc |
| S_CBRANCH_SCC0 %bb.4, implicit $scc |
| |
| bb.2: |
| %4:sreg_64_xexec = V_CMP_NE_U32_e64 1, %2, implicit $exec |
| $vcc = S_AND_B64 $exec, %4, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| S_BRANCH %bb.3 |
| |
| bb.3: |
| S_BRANCH %bb.1 |
| |
| bb.4: |
| ... |
| |
| --- |
| name: cndmask_loop_cndmask_split |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_loop_cndmask_split |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc |
| ; CHECK-NEXT: S_BRANCH %bb.2 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.5(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.5 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF1]], implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.4(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], -1, implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.5, implicit $scc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| ; CHECK-NEXT: successors: %bb.2(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BRANCH %bb.2 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.5: |
| bb.0: |
| $vcc = IMPLICIT_DEF |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| %1:sreg_32 = IMPLICIT_DEF |
| %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| S_CBRANCH_VCCZ %bb.5, implicit $vcc |
| S_BRANCH %bb.1 |
| |
| bb.5: |
| S_BRANCH %bb.4 |
| |
| bb.1: |
| %4:sreg_64_xexec = V_CMP_NE_U32_e64 1, %2, implicit $exec |
| $vcc = S_AND_B64 $exec, %4, implicit-def $scc |
| S_CBRANCH_VCCNZ %bb.3, implicit $vcc |
| |
| bb.2: |
| %1:sreg_32 = S_ADD_I32 %1, -1, implicit-def $scc |
| S_CBRANCH_SCC0 %bb.4, implicit $scc |
| |
| bb.3: |
| S_BRANCH %bb.1 |
| |
| bb.4: |
| ... |
| |
| # We would need to extend the live range of %0 to be live out of %bb.2 |
| |
| --- |
| name: register_not_marked_liveout |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' |
| stackPtrOffsetReg: '$sgpr32' |
| returnsVoid: true |
| body: | |
| ; CHECK-LABEL: name: register_not_marked_liveout |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 |
| ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec |
| ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 0, [[V_CNDMASK_B32_e64_]], implicit $exec |
| ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]] |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]] |
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[S_MOV_B64_]], implicit-def dead $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| bb.0: |
| liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| |
| %0:sreg_64_xexec = S_MOV_B64 0 |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %2:sreg_64 = V_CMP_GT_I32_e64 0, %1, implicit $exec |
| $exec = S_MOV_B64_term %2 |
| |
| bb.1: |
| $exec = S_MOV_B64_term %2 |
| S_CBRANCH_EXECZ %bb.3, implicit $exec |
| |
| bb.2: |
| %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc |
| S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc |
| |
| bb.3: |
| |
| ... |
| |
| # Can't delete V_CNDMASK_B32 when folding into the use in %bb.3 since |
| # it's also used in %bb.0 |
| --- |
| name: cndmask_multiple_uses |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: cndmask_multiple_uses |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec |
| ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.3(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.5, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.4(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def dead $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.5, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.4: |
| ; CHECK-NEXT: successors: %bb.5(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.5: |
| bb.0: |
| liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| |
| %0:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec |
| %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %0, implicit $exec |
| |
| bb.1: |
| S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc |
| |
| bb.2: |
| $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc |
| S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc |
| |
| bb.3: |
| %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %0, implicit $exec |
| $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc |
| S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc |
| |
| bb.5: |
| |
| bb.6: |
| |
| ... |
| |
| # The live segment of %1 from V_CMP_GT_I32 needs to be shrunk after the use in %bb.1 is deleted |
| --- |
| name: leftover_use_of_selreg_extends_liverange |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: leftover_use_of_selreg_extends_liverange |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec |
| ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 0, [[V_CNDMASK_B32_e64_]], implicit $exec |
| ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]] |
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def dead $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| bb.0: |
| liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %2:sreg_64 = V_CMP_GT_I32_e64 0, %1, implicit $exec |
| $exec = S_MOV_B64_term %2 |
| S_CBRANCH_EXECZ %bb.2, implicit $exec |
| |
| bb.1: |
| %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec |
| $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc |
| S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc |
| |
| bb.2: |
| |
| bb.3: |
| |
| ... |
| |
| --- |
| name: leftover_use_of_selreg_extends_liverange_subrange |
| tracksRegLiveness: true |
| body: | |
| ; CHECK-LABEL: name: leftover_use_of_selreg_extends_liverange_subrange |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF |
| ; CHECK-NEXT: undef %1.sub1:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec |
| ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 0, %1.sub1, implicit $exec |
| ; CHECK-NEXT: %1.sub0:vreg_64 = V_MOV_B32_e32 123, implicit $exec |
| ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]] |
| ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def dead $scc |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_NOP 0, implicit %1.sub0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| bb.0: |
| liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16 |
| |
| %0:sreg_64_xexec = IMPLICIT_DEF |
| undef %1.sub1:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec |
| %1.sub0 = V_MOV_B32_e32 123, implicit $exec |
| %2:sreg_64 = V_CMP_GT_I32_e64 0, %1.sub1, implicit $exec |
| $exec = S_MOV_B64_term %2 |
| S_CBRANCH_EXECZ %bb.2, implicit $exec |
| |
| bb.1: |
| %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1.sub1, implicit $exec |
| $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc |
| S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc |
| |
| bb.2: |
| S_NOP 0, implicit %1.sub0 |
| |
| bb.3: |
| |
| ... |