test/CodeGen/AMDGPU/hazard-lds-addtid.mir

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,GFX9
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN
---

# GCN-LABEL: name: addtid

# GCN-LABEL: bb.0:
# GCN: S_MOV_B32
# GFX9-NEXT: S_NOP
# GCN-NEXT: DS_WRITE_ADDTID_B32

# GCN-LABEL: bb.1:
# GCN: S_MOV_B32
# GFX9-NEXT: S_NOP
# GCN-NEXT: DS_READ_ADDTID_B32

# GCN-LABEL: bb.2:
# GCN: S_MOV_B32
# GFX9-NEXT: S_NOP
# GCN-NEXT: DS_WRITE_ADDTID_B32

# GCN-LABEL: bb.3:
# GCN: S_MOV_B32
# GFX9-NEXT: S_NOP
# GCN-NEXT: DS_READ_ADDTID_B32

name: addtid

body: |
  bb.0:
    $m0 = S_MOV_B32 0
    DS_WRITE_ADDTID_B32 killed $vgpr0, 0, 0, implicit $m0, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    $m0 = S_MOV_B32 0
    $vgpr0 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec
    S_BRANCH %bb.2

  bb.2:
    $m0 = S_MOV_B32 0
    DS_WRITE_ADDTID_B32 killed $vgpr0, 0, 0, implicit $m0, implicit $exec
    S_BRANCH %bb.3

  bb.3:
    $m0 = S_MOV_B32 0
    $vgpr0 = DS_READ_ADDTID_B32 0, 0, implicit $m0, implicit $exec
    S_ENDPGM 0
...