test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

define void @st1d_fixed(<8 x double>* %ptr) #0 {
; CHECK-LABEL: st1d_fixed:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    add x8, sp, #8
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    ld2d { z0.d, z1.d }, p0/z, [x8]
; CHECK-NEXT:    mov x8, #4
; CHECK-NEXT:    mov z0.d, #0 // =0x0
; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
; CHECK-NEXT:    st1d { z0.d }, p0, [x0, x8, lsl #3]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
  %alloc = alloca [16 x double], i32 0
  %bc = bitcast [16 x double]* %alloc to <8 x double>*
  %load = load <8 x double>, <8 x double>* %bc
  %strided.vec = shufflevector <8 x double> %load, <8 x double> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  store <8 x double> zeroinitializer, <8 x double>* %ptr
  ret void
}

attributes #0 = { "target-features"="+sve" vscale_range(2,2) nounwind }