test/CodeGen/AArch64/andandshift.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 < %s | FileCheck %s

target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "arm64--linux-gnu"

; Function Attrs: nounwind readnone
define i32 @test1(i8 %a) {
; CHECK-LABEL: test1:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ubfx w0, w0, #3, #5
; CHECK-NEXT:    ret
entry:
  %conv = zext i8 %a to i32
  %shr1 = lshr i32 %conv, 3
  ret i32 %shr1
}

; Function Attrs: nounwind readnone
define i32 @test2(i8 %a) {
; CHECK-LABEL: test2:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    and w8, w0, #0xff
; CHECK-NEXT:    ubfx w9, w0, #3, #5
; CHECK-NEXT:    cmp w8, #47
; CHECK-NEXT:    csel w0, w9, w8, hi
; CHECK-NEXT:    ret
entry:
  %conv = zext i8 %a to i32
  %cmp = icmp ugt i8 %a, 47
  %shr5 = lshr i32 %conv, 3
  %retval.0 = select i1 %cmp, i32 %shr5, i32 %conv
  ret i32 %retval.0
}