| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s |
| |
| --- |
| name: div_fmas_sss_scc |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 |
| ; CHECK-LABEL: name: div_fmas_sss_scc |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] |
| ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) |
| ; CHECK: [[COPY7:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s1) |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s32) = COPY $sgpr1 |
| %2:_(s32) = COPY $sgpr2 |
| %3:_(s32) = COPY $sgpr3 |
| %4:_(s32) = G_CONSTANT i32 0 |
| %5:_(s1) = G_ICMP intpred(eq), %3, %4 |
| %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5 |
| ... |
| |
| --- |
| name: div_fmas_sss_vcc |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0 |
| ; CHECK-LABEL: name: div_fmas_sss_vcc |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) |
| ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]] |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[ICMP]](s1) |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s32) = COPY $sgpr1 |
| %2:_(s32) = COPY $sgpr2 |
| %3:_(s32) = COPY $vgpr0 |
| %4:_(s32) = G_CONSTANT i32 0 |
| %5:_(s1) = G_ICMP intpred(eq), %3, %4 |
| %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5 |
| ... |
| |
| --- |
| name: div_fmas_vss_vcc |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr1 |
| ; CHECK-LABEL: name: div_fmas_vss_vcc |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) |
| ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]] |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY5]](s32), [[COPY6]](s32), [[ICMP]](s1) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $sgpr0 |
| %2:_(s32) = COPY $sgpr1 |
| %3:_(s32) = COPY $vgpr1 |
| %4:_(s32) = G_CONSTANT i32 0 |
| %5:_(s1) = G_ICMP intpred(eq), %3, %4 |
| %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5 |
| ... |
| |
| --- |
| name: div_fmas_vvv_vcc |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 |
| ; CHECK-LABEL: name: div_fmas_vvv_vcc |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) |
| ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]] |
| ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[ICMP]](s1) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = COPY $vgpr3 |
| %4:_(s32) = G_CONSTANT i32 0 |
| %5:_(s1) = G_ICMP intpred(eq), %3, %4 |
| %6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5 |
| ... |