| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s |
| # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s |
| |
| --- |
| name: fmul_v2f16_vv |
| legalized: true |
| regBankSelected: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; GFX9-LABEL: name: fmul_v2f16_vv |
| ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; GFX9: %2:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec |
| ; GFX9: S_ENDPGM 0, implicit %2 |
| %0:vgpr(<2 x s16>) = COPY $vgpr0 |
| %1:vgpr(<2 x s16>) = COPY $vgpr1 |
| %2:vgpr(<2 x s16>) = G_FMUL %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: fmul_v2f16_fneg_v_fneg_v |
| legalized: true |
| regBankSelected: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v |
| ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; GFX9: %4:vgpr_32 = nofpexcept V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec |
| ; GFX9: S_ENDPGM 0, implicit %4 |
| %0:vgpr(<2 x s16>) = COPY $vgpr0 |
| %1:vgpr(<2 x s16>) = COPY $vgpr1 |
| %2:vgpr(<2 x s16>) = G_FNEG %0 |
| %3:vgpr(<2 x s16>) = G_FNEG %1 |
| %4:vgpr(<2 x s16>) = G_FMUL %2, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: fmul_v2f16_fneg_lo_v_v |
| legalized: true |
| regBankSelected: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v |
| ; GFX9: [[COPY:%[0-9]+]]:vgpr_32(<2 x s16>) = COPY $vgpr0 |
| ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 |
| ; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 |
| ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32) |
| ; GFX9: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]] |
| ; GFX9: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16) |
| ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:vgpr_32(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY2]](s32) |
| ; GFX9: %7:vgpr_32(<2 x s16>) = nofpexcept V_PK_MUL_F16 8, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 8, [[COPY]](<2 x s16>), 0, 0, 0, 0, 0, implicit $mode, implicit $exec |
| ; GFX9: S_ENDPGM 0, implicit %7(<2 x s16>) |
| %0:vgpr(<2 x s16>) = COPY $vgpr0 |
| %1:vgpr(s32) = COPY $vgpr1 |
| %2:vgpr(s32) = COPY $vgpr2 |
| %3:vgpr(s16) = G_TRUNC %1 |
| %4:vgpr(s16) = G_FNEG %3 |
| %5:vgpr(s32) = G_ANYEXT %4 |
| %6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2 |
| %7:vgpr(<2 x s16>) = G_FMUL %6, %0 |
| S_ENDPGM 0, implicit %7 |
| ... |