test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1  | FileCheck -check-prefix=ERR %s

# Make sure incorrect usage of control flow intrinsics fails to select in case some transform separated the intrinsic from its branch.

# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_xor_0)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_or_neg1)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_negated_multi_use)


---
name: brcond_si_if_different_block
body:             |
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2

  bb.1:
      G_BRCOND %3, %bb.1

...

---
name: si_if_not_brcond_user
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
    %5:_(s32) = G_SELECT %3, %0, %1
    S_ENDPGM 0, implicit %5

...

---
name: si_if_multi_user
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
    %5:_(s32) = G_SELECT %3, %0, %1
    G_BRCOND %3, %bb.1

  bb.1:
    S_ENDPGM 0, implicit %5

...

# Make sure we only match G_XOR (if), -1
---
name: brcond_si_if_xor_0
body:             |
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
    %5:_(s1) = G_CONSTANT i1 false
    %6:_(s1) = G_XOR %3, %5
    G_BRCOND %6, %bb.2
    G_BR %bb.3

  bb.1:
    S_NOP 0

  bb.2:
    S_NOP 1

  bb.3:
    S_NOP 2
...

# Make sure we only match G_XOR (if), -1
---
name: brcond_si_if_or_neg1
body:             |
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
    %5:_(s1) = G_CONSTANT i1 true
    %6:_(s1) = G_OR %3, %5
    G_BRCOND %6, %bb.2
    G_BR %bb.3

  bb.1:
    S_NOP 0

  bb.2:
    S_NOP 1

  bb.3:
    S_NOP 2
...

---
name: brcond_si_if_negated_multi_use
body:             |
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
    %5:_(s1) = G_CONSTANT i1 true
    %6:_(s1) = G_XOR %3, %5
    S_NOP 0, implicit %6
    G_BRCOND %6, %bb.2
    G_BR %bb.3

  bb.1:
    S_NOP 0

  bb.2:
    S_NOP 1

  bb.3:
    S_NOP 2
...