| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s |
| |
| # These violate the constant bus restriction pre-gfx10 |
| |
| --- |
| name: uadde_s32_s1_vsv |
| legalized: true |
| regBankSelected: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| |
| ; GFX10-LABEL: name: uadde_s32_s1_vsv |
| ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; GFX10: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec |
| ; GFX10: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec |
| ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; GFX10: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec |
| ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec |
| ; GFX10: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:vgpr(s32) = COPY $vgpr0 |
| %2:vgpr(s32) = COPY $vgpr2 |
| %3:vgpr(s32) = G_CONSTANT i32 0 |
| %4:vcc(s1) = G_ICMP intpred(eq), %2, %3 |
| %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4 |
| %7:vgpr(s32) = G_CONSTANT i32 0 |
| %8:vgpr(s32) = G_CONSTANT i32 1 |
| %9:vgpr(s32) = G_SELECT %6, %7, %8 |
| S_ENDPGM 0, implicit %5, implicit %9 |
| ... |
| |
| --- |
| name: uadde_s32_s1_vvs |
| legalized: true |
| regBankSelected: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| |
| ; GFX10-LABEL: name: uadde_s32_s1_vvs |
| ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; GFX10: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec |
| ; GFX10: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec |
| ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; GFX10: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec |
| ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec |
| ; GFX10: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]] |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr(s32) = COPY $sgpr0 |
| %2:vgpr(s32) = COPY $vgpr2 |
| %3:vgpr(s32) = G_CONSTANT i32 0 |
| %4:vcc(s1) = G_ICMP intpred(eq), %2, %3 |
| %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4 |
| %7:vgpr(s32) = G_CONSTANT i32 0 |
| %8:vgpr(s32) = G_CONSTANT i32 1 |
| %9:vgpr(s32) = G_SELECT %6, %7, %8 |
| S_ENDPGM 0, implicit %5, implicit %9 |
| ... |