test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s

---

name:            and_or_s32_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr2
    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
    ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
    ; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_]]
    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
    ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
    ; GFX9: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = COPY $sgpr2
    %3:sgpr(s32) = G_AND %0, %1
    %4:sgpr(s32) = G_OR %3, %2
    S_ENDPGM 0, implicit %4
...

---

name:            and_or_s32_vgpr_vgpr_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2
    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[COPY2]], implicit $exec
    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(s32) = G_AND %0, %1
    %4:vgpr(s32) = G_OR %3, %2
    S_ENDPGM 0, implicit %4
...

---

name:            and_or_s32_vgpr_vgpr_vgpr_commute
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2
    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY2]], [[V_AND_B32_e64_]], implicit $exec
    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(s32) = G_AND %0, %1
    %4:vgpr(s32) = G_OR %2, %3
    S_ENDPGM 0, implicit %4
...

---

name:            and_or_s32_sgpr_sgpr_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $vgpr0
    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
    ; GFX8: liveins: $sgpr0, $sgpr1, $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
    ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
    ; GFX9: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
    ; GFX9: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:vgpr(s32) = COPY $vgpr0
    %3:sgpr(s32) = G_AND %0, %1
    %4:vgpr(s32) = COPY %3
    %5:vgpr(s32) = G_OR %4, %2
    S_ENDPGM 0, implicit %5
...