test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s

---
name: intrinsic_trunc_s16_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: intrinsic_trunc_s16_vv
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: %2:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN: $vgpr0 = COPY %2
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_INTRINSIC_TRUNC %1
    %3:vgpr(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: intrinsic_trunc_s16_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: intrinsic_trunc_s16_vs
    ; GCN: liveins: $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: %2:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN: $vgpr0 = COPY %2
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_INTRINSIC_TRUNC %1
    %3:vgpr(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: intrinsic_trunc_fneg_s16_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: intrinsic_trunc_fneg_s16_vv
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: %3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN: $vgpr0 = COPY %3
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_FNEG %1
    %3:vgpr(s16) = G_INTRINSIC_TRUNC %2
    %4:vgpr(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...