test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s

---
name: insert_vector_elt_s_s32_v2s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v2s32
    ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v2s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
    %1:sgpr(s32) = COPY $sgpr2
    %2:sgpr(s32) = COPY $sgpr3
    %3:sgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s32_v3s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v3s32
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v3s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
    %0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
    %1:sgpr(s32) = COPY $sgpr3
    %2:sgpr(s32) = COPY $sgpr4
    %3:sgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s32_v4s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
    %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:sgpr(s32) = COPY $sgpr3
    %2:sgpr(s32) = COPY $sgpr4
    %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s32_v5s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v5s32
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v5s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
    %0:sgpr(<5 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
    %1:sgpr(s32) = COPY $sgpr5
    %2:sgpr(s32) = COPY $sgpr6
    %3:sgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s32_v8s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    %1:sgpr(s32) = COPY $sgpr8
    %2:sgpr(s32) = COPY $sgpr9
    %3:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s32_v16s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v16s32
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v16s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]]
    %0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
    %1:sgpr(s32) = COPY $sgpr16
    %2:sgpr(s32) = COPY $sgpr17
    %3:sgpr(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: extract_vector_elt_s_s32_v32s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41

    ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v32s32
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]]
    ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]]
    %0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
    %1:sgpr(s32) = COPY $sgpr40
    %2:sgpr(s32) = COPY $sgpr41
    %3:sgpr(<32 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s64_v2s64
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6

    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v2s64
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v2s64
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
    %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:sgpr(s64) = COPY $sgpr4_sgpr5
    %2:sgpr(s32) = COPY $sgpr6
    %3:sgpr(<2 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s64_v4s64
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10

    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v4s64
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v4s64
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
    %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    %1:sgpr(s64) = COPY $sgpr8_sgpr9
    %2:sgpr(s32) = COPY $sgpr10
    %3:sgpr(<4 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_s_s64_v8s64
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18

    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v8s64
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v8s64
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
    %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
    %1:sgpr(s64) = COPY $sgpr16_sgpr17
    %2:sgpr(s32) = COPY $sgpr18
    %3:sgpr(<8 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: extract_vector_elt_s_s64_v16s64
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42

    ; MOVREL-LABEL: name: extract_vector_elt_s_s64_v16s64
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
    ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
    %0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
    %1:sgpr(s64) = COPY $sgpr40_sgpr41
    %2:sgpr(s32) = COPY $sgpr42
    %3:sgpr(<16 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_vvs_s32_v2s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v2s32
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v2s32
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_]]
    %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:vgpr(s32) = COPY $vgpr2
    %2:sgpr(s32) = COPY $sgpr3
    %3:vgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_vvs_s32_v3s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v3s32
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v3s32
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_]]
    %0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:vgpr(s32) = COPY $vgpr3
    %2:sgpr(s32) = COPY $sgpr4
    %3:vgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_vvs_s32_v4s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v4s32
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v4s32
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]]
    %0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:vgpr(s32) = COPY $vgpr3
    %2:sgpr(s32) = COPY $sgpr4
    %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_vvs_s32_v5s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v5s32
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v5s32
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_]]
    %0:vgpr(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
    %1:vgpr(s32) = COPY $vgpr5
    %2:sgpr(s32) = COPY $sgpr6
    %3:vgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_vvs_s32_v8s32
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:vgpr(s32) = COPY $vgpr8
    %2:sgpr(s32) = COPY $sgpr9
    %3:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_vvs_s32_v8s32_add_1
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 11, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:vgpr(s32) = COPY $vgpr8
    %2:sgpr(s32) = COPY $sgpr9
    %3:sgpr(s32) = G_CONSTANT i32 1
    %4:sgpr(s32) = G_ADD %2, %3
    %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
    S_ENDPGM 0, implicit %5
...

---
name: insert_vector_elt_vvs_s32_v8s32_add_8
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9

    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
    ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
    ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
    ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[S_ADD_I32_]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:vgpr(s32) = COPY $vgpr8
    %2:sgpr(s32) = COPY $sgpr9
    %3:sgpr(s32) = G_CONSTANT i32 8
    %4:sgpr(s32) = G_ADD %2, %3
    %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
    S_ENDPGM 0, implicit %5
...

---
name: insert_vector_elt_s_s32_v8s32_add_1
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; MOVREL: $m0 = COPY [[COPY2]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; GPRIDX: $m0 = COPY [[COPY2]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    %1:sgpr(s32) = COPY $sgpr8
    %2:sgpr(s32) = COPY $sgpr9
    %3:sgpr(s32) = G_CONSTANT i32 1
    %4:sgpr(s32) = G_ADD %2, %3
    %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
    S_ENDPGM 0, implicit %5
...

---
name: insert_vector_elt_s_s32_v8s32_add_8
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
    ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
    ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
    ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
    ; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
    %1:sgpr(s32) = COPY $sgpr8
    %2:sgpr(s32) = COPY $sgpr9
    %3:sgpr(s32) = G_CONSTANT i32 8
    %4:sgpr(s32) = G_ADD %2, %3
    %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
    S_ENDPGM 0, implicit %5
...

# This should have been folded out in the legalizer, but make sure it
# doesn't crash.
---
name: insert_vector_elt_s_s32_v4s32_const_idx
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4

    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; MOVREL: $m0 = COPY [[S_MOV_B32_]]
    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GPRIDX: $m0 = COPY [[S_MOV_B32_]]
    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
    %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:sgpr(s32) = COPY $sgpr4
    %2:sgpr(s32) = G_CONSTANT i32 0
    %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_v_s32_v4s32_const_idx
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4

    ; MOVREL-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
    ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; MOVREL: $m0 = COPY [[S_MOV_B32_]]
    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
    ; GPRIDX-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[S_MOV_B32_]], 3, implicit-def $m0, implicit $m0, implicit $exec
    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]]
    %0:vgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:sgpr(s32) = COPY $sgpr4
    %2:sgpr(s32) = G_CONSTANT i32 0
    %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...