test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s


---
name:            atomicrmw_xchg_s32_region
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: atomicrmw_xchg_s32_region
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: $m0 = S_MOV_B32 -1
    ; GFX6: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
    ; GFX6: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
    ; GFX7-LABEL: name: atomicrmw_xchg_s32_region
    ; GFX7: liveins: $vgpr0, $vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: $m0 = S_MOV_B32 -1
    ; GFX7: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
    ; GFX7: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
    ; GFX9-LABEL: name: atomicrmw_xchg_s32_region
    ; GFX9: liveins: $vgpr0, $vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
    ; GFX9: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
    %0:vgpr(p2) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_ATOMICRMW_XCHG %0(p2), %1 :: (load store seq_cst 4, addrspace 2)
    $vgpr0 = COPY %2

...

---
name:            atomicrmw_xchg_s32_region_gep4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: atomicrmw_xchg_s32_region_gep4
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
    ; GFX6: %3:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
    ; GFX6: $m0 = S_MOV_B32 -1
    ; GFX6: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 %3, [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
    ; GFX6: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
    ; GFX7-LABEL: name: atomicrmw_xchg_s32_region_gep4
    ; GFX7: liveins: $vgpr0, $vgpr1
    ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: $m0 = S_MOV_B32 -1
    ; GFX7: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
    ; GFX7: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
    ; GFX9-LABEL: name: atomicrmw_xchg_s32_region_gep4
    ; GFX9: liveins: $vgpr0, $vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
    ; GFX9: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
    %0:vgpr(p2) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_CONSTANT i32 4
    %3:vgpr(p2) = G_PTR_ADD %0, %2
    %4:vgpr(s32) = G_ATOMICRMW_XCHG %3(p2), %1 :: (load store seq_cst 4, addrspace 2)
    $vgpr0 = COPY %4

...