test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            test_const_const
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_const_const
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
    ; CHECK: $sgpr0 = COPY [[C]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = G_CONSTANT i32 15
    %1:_(s32) = G_CONSTANT i32 255
    %2:_(s32) = G_AND %0(s32), %1(s32)
    $sgpr0 = COPY %2(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0
...

---
name:            test_const_const_2
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_const_const_2
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
    ; CHECK: $sgpr0 = COPY [[C]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = G_CONSTANT i32 255
    %1:_(s32) = G_CONSTANT i32 15
    %2:_(s32) = G_AND %0(s32), %1(s32)
    $sgpr0 = COPY %2(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0
...

---
name:            test_const_const_3
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_const_const_3
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
    ; CHECK: $vgpr0 = COPY [[C]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = G_CONSTANT i32 2863311530
    %1:_(s32) = G_CONSTANT i32 4008636142
    %2:_(s32) = G_AND %0(s32), %1(s32)
    $vgpr0 = COPY %2(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0
...

---
name:            test_and_and
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_and_and
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK: $vgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 15
    %2:_(s32) = G_CONSTANT i32 255
    %3:_(s32) = G_AND %0, %1(s32)
    %4:_(s32) = G_AND %3, %2
    $vgpr0 = COPY %4(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0
...

---
name:            test_shl_and
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: test_shl_and
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
    ; CHECK: $sgpr0 = COPY [[SHL]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_CONSTANT i32 5
    %2:_(s32) = G_CONSTANT i32 4294967264
    %3:_(s32) = G_SHL %0, %1(s32)
    %4:_(s32) = G_AND %3, %2
    $sgpr0 = COPY %4(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0
...

---
name:            test_lshr_and
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_lshr_and
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 5
    %2:_(s32) = G_CONSTANT i32 134217727
    %3:_(s32) = G_LSHR %0, %1(s32)
    %4:_(s32) = G_AND %3, %2
    $vgpr0 = COPY %4(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0
...

---
name:            test_and_non_const
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: test_and_non_const
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
    ; CHECK: $sgpr0 = COPY [[LSHR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_CONSTANT i32 16
    %3:_(s32) = G_CONSTANT i32 65535
    %4:_(s32) = G_OR %1, %3
    %5:_(s32) = G_LSHR %0, %2(s32)
    %6:_(s32) = G_AND %5, %4
    $sgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name:            test_sext_inreg
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_sext_inreg
    ; CHECK: %cst_1:_(s32) = G_CONSTANT i32 -5
    ; CHECK: $sgpr0 = COPY %cst_1(s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %cst_1:_(s32) = G_CONSTANT i32 -5

    ; 000 ... 1011
    %cst_11:_(s32) = G_CONSTANT i32 11

    ; Sext from the 4th bit -> 111 ... 1011 = -5
    %sext_inreg_11:_(s32) = G_SEXT_INREG %cst_11, 4

    %and:_(s32) = G_AND %cst_1(s32), %sext_inreg_11(s32)
    $sgpr0 = COPY %and(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0
...