test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
---
name:            fadd_v2s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: fadd_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[FADDPv2i32p:%[0-9]+]]:fpr32 = FADDPv2i32p [[COPY]]
    ; CHECK: $w0 = COPY [[FADDPv2i32p]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(s32) = G_VECREDUCE_FADD %0(<2 x s32>)
    $w0 = COPY %1(s32)
    RET_ReallyLR implicit $w0

...
---
name:            fadd_v2s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: fadd_v2s64
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[FADDPv2i64p:%[0-9]+]]:fpr64 = FADDPv2i64p [[COPY]]
    ; CHECK: $x0 = COPY [[FADDPv2i64p]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:fpr(<2 x s64>) = COPY $q0
    %2:fpr(s64) = G_VECREDUCE_FADD %0(<2 x s64>)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...